Home Page: TRAVEO™ T2G Automotive Body Controller - FAQ – CDC
10. Interrupts
10.1. How can I understand the priority configuration in the NVIC_IPR register?
For a basic understanding of the NVIC_IPR register, see the Arm documentation.
Here is an extract from the Arm documentation - “The priority registers are stored with the Most Significant Bit (MSB) first. This means that if there are four bits of priority, the priority value is stored in bits [7:4] of the byte. However, if there are three bits of priority, the priority value is stored in bits [7:5] of the byte. This means that an application can work even if it does not know how many priorities are possible.”
Illustration1:
CM0+ - Priority values are from 0 to 3. Consider that priority is being configured only for IRQ0. Priorities of other interrupts will remain 0.
Bits [7:0] correspond to the priority of IRQ0. Here, priority levels 0 to 3 need only 2 bits. So, priority is stored in Bits [7:6]. Other values are ignored.
Priority level and the corresponding IPR0 register values are as below:
0 – 0x00000000 1 – 0x00000040
2 – 0x00000080 3 – 0x000000C0
Illustration 2:
CM4 - Priority values are from 0 to 7. Consider that priority is being configured only for IRQ0. Priorities of other interrupts will remain 0.
Bits [7:0] correspond to the priority of IRQ0. Here, priority levels 0 to 7 need only 3 bits. So, priority is stored in Bits [7:5]. Other values are ignored.
Priority level and the corresponding IPR0 register values are as below:
0 – 0x00000000 1 – 0x00000020
2 – 0x00000040 3 – 0x00000060
4 – 0x00000080 5 – 0x000000A0
6 – 0x000000C0 7 – 0x000000E0
10.2. Is there a way to generate interrupt between the cores without using IPC?
Generally, IPC is used for synchronization between the core. But if the IPC resources are exhausted, any other interrupt unused peripherals can be used for synchronization between the cores by triggering the interrupt of the using software.