1.1.How do I connect ADC output triggers to a TCPWM?
1.2.How do I start ADC conversions using TCPWM output triggers?
1.3.How do I pause the TCPWM block?
1.4.What is the behavior when there are more than two bits error on ECC memory?
1.5.Can BACKUP_BREGx contents be retained after software reset?
1.6.How can HyperRAM be connected to Traveo II Body High?
1.7.What are the precautions to be followed when using Socketed CPU board?
1.8.Do different SMIF channels have different graphics performance?
1.9.What is the reserved SRAM in memory map of CYTx devices?
2.1.What is the status of unused GPIO pins?
2.2.Which GPIO port is available for Slew Rate Control?
2.3.Is the GPIO pin connected to the Stepper Motor directly?
2.4.If CAN and LIN are connected, which are used: GPIO_STD or GPIO_ENH?
2.5.What value can be used as output impedance of the GPIO for impedance matching?
2.6.If one pin of the device has been used as the input of Smart I/O, can the same pin be used for the output of other peripheral blocks?
2.7.If the pad of one pin is not available on a certain package, can its alternate function be routed to Smart I/O?
2.8.Why cannot SMIF HSIO_ENH pins be configured as GPIO?
3.1. What is the drive mode for SCB in DeepSleep mode?
3.2. Does SCB SPI support Quad SPI protocol?
3.3. What is the maximum clock speed of SCB SPI of CYT2B/CYT4B?
4.1. What is the use of analog calibration in ADC? How is it performed?
4.2. What is ADC pre-conditioning? Where is it used?
4.3. As per the datasheet, up to 32 analog pins can be connected to the SARMUX inputs. Can I connect more external inputs to the same ADC?
4.4. How do we configure the sample time for the ADC channel? What is the appropriate value for the sample time?
4.5. What is the ADC channel group?
4.6. What is ADC trigger? What are different trigger options for the SAR ADC in Traveo II?
4.7. What are VREFH and VREFL?
4.8. Is it possible to use a voltage that is or is derived from the 0.9 V band gap voltage as reference voltage for an AD conversion?
4.9. After PASSx_SARy_CHz_TR_CMD.START is set, ADC conversion stopped. What could be the reason?
4.10. Does SAR ADC in Traveo II support self-diagnostic feature, that is, does it contain any diagnostic register which is set when there is any short or open circuit fault?
5.1. How do I start building Traveo II IAR projects in the Sample Driver Library (SDL)?
5.2. How do I change the MPN for the device under test in the SDL GHS project?
5.3. How can I perform operations on the device using Miniprog4 and Auto Flash Utility?
5.4. Can I use MiniProg4 tool for debugging beside flashing and erasing?
5.5. Is it possible to use GDB with Traveo II? If yes, how can I set it up?
5.6. I have installed the Cypress Sample Driver Library (SDL) and but I am unable to flash or debug the example project even after successful build. What could be the reason?
6.1. Do Traveo II Body Entry Controllers have cache?
6.2. I am unable to access certain FM_CTL_ECT registers. What could be the reason?
6.3. What is the CodeFlash and WorkFlash in Traveo II?
6.4. What is the eCT Flash in Traveo II?
6.5. What is the operation size number of Traveo II CodeFlash and WorkFlash?
6.6. Is Traveo II Flash operation available in low power modes?
6.7. What happens if WorkFlash is read immediately after erasing (that is, before its initialization)?
6.8. Can Blank Check command be used for Code Flash?
6.9. How can I check if the “1-bit” ECC error is due to reading a blank location or if there was an actual ECC error?
7.1. Is there a way to prevent the program execution from an unused region of memory?
7.2. Do Traveo II Body High devices support exclusive memory instructions?
7.3. I am unable to write to the M7 CPU registers like VTOR and TCM-related registers. What could be the reason?
7.4. What is the purpose of CPUSS_CM0_PC_CTL and CPUSS_CM0_PCx_HANDLER registers?
7.5. What is the status of the CM4/7 cores after the boot process?
8.1. I am unable to get proper baud rate for LIN. How is the LIN baud rate is calculated from the peripheral clock?
9.1. Is it possible to configure a P-DMA channel (for instance, P-DMA0), while the P-DMA peripheral is enabled globally? Should the P-DMA instance be globally disabled before configuring a particular channel?
10.1. How can I understand the priority configuration in the NVIC_IPR register?
10.2. Is there a way to generate interrupt between the cores without using IPC?
11.1. What is eSHE and HSM of Traveo II?
11.2. How do I perform Authenticated Debugging in CYTx devices?
11.3. What is the state of the SWPU when the device goes to DeepSleep state?
11.4. Can the CyBAF used in SECURE protection stage?
11.5. How are the device keys in the Traveo II devices generated?
11.6. How can the flash update be prevented for specific region?
11.7. What are the pitfalls to be considered during configuration of SMPU?
12. Power mode
12.1. Can the IMO be turned off before transitioning to deep-sleep mode?
12.2. The device enters deep-sleep mode only when LPM_READY bit of the PWR_CTL is 1, when does this bit 0?
12.3. What is the state of the registers when the device goes to DeepSleep state?
12.4. What is the recommended state of debug pins before entry into DeepSleep?
12.5. Should the SleepDeep bit be set on both cores before executing WFI in both cores to enter DeepSleep?
13.1. How do I configure ECO?
13.2. As the peripherals in Traveo II are organized as group and slaves, how would I know the clock tree mapping for these peripheral with respect to group and slave?
13.3. Are there any precautions to be taken while switching the clock source?
13.4. What happens if ECO is short circuited or not populated?
13.5. How many HF paths are allowed to connect to one PLL?
14. Boot and System call
14.1. How can I check if IRQ0/IRQ1 is configured properly, if SROM API or System call is not working?
14.2. How do I program the eFuse memory?
14.3. Can the flash operations be cancelled after initiating?
14.4. Which part of the SRAM can be used for the internal bootloader?
14.5. Can CySAF be used in NORMAL protection stage to perform authentication?
14.6. How can the start address of an application be relocated during startup after reset?
14.7. Can System Call of Cy_FB_VerifyApplication be used as a standalone (that is. without SLLD)? In this case, is the Public key same as the key used in Flash boot?
15.1. How can the I2C configuration be evaluated based on actual Bus conditions?
16.1. How can the index of TCPWM channel be calculated?
17.1. Is it mandatory to check the VALID bit when a fault interrupt occurs?
18.1. What is the clock source for watchdog of Traveo II devices?
18.2. How can the RESET triggered by WDTs be issued?
18.3. How can the watchdogs of Traveo II devices be enabled?
19.1. What is the tolerance of RTC in Traveo II device?