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Question: What are the differences in the TCPWM block of the CY8C62x4 devices compared to other PSoC 6 MCU devices?
Answer: Note: This article presumes the reader has an in-depth knowledge of the TCPWM block in PSoC 6 MCU devices and its various operational modes.
CY8C62x4 (PSoC 6 MCU with 256K flash) devices have a new version of the TCPWM block that is targeted mainly for motor control applications, and Field-Oriented Control (FOC) in particular.
The following is a list of major changes that support this application and their intended example usage:
Second Capture / Compare function The CY8C62x4 TCPWM block has two compare/capture registers (CC0 and CC1), while the block in other PSoC 6 MCU devices have only one. The functionalities of both CC0 and CC1 are the same. A typical application is the generation of asymmetric PWM signals with a lower CPU load (compared to generation using a single CC function). These signals are widely used in motor control applications for enabling single-shunt current measurement.
Immediate PWM kill The kill input is synchronized with a faster peripheral clock, while in other PSoC 6 MCU devices, it is a slow counter clock. This gives a better response time in emergency situations to kill the PWM signal, such as a short circuit in the motor control application.
Second kill input trigger The TCPWM block in CY8C62x4 has two kill input triggers, while the block in other PSoC 6 MCU devices have only one. A common kill input can be selected from the trigger multiplexer block, for allowing synchronous stop/kill operation of multiple PWMs. The dedicated ADC out-of-range trigger can be selected as the additional kill input for allowing real-time hardware stop of a PWM signal.
Independent dead times for line and complementary line output signals In CY8C62x4, the PWM line and complementary line output signals can be configured to have different dead times, while in other PSoC 6 MCUs, both outputs have a common dead time. Dead time is used to prevent short circuits in motor control applications. This feature gives more control over the gap between outputs.
Compare match events can be enabled/disabled independently while counter is up or down counting The CY8C62x4 TCPWM block has two compare/capture registers (CC0 and CC1) as explained previously. When the counter is configured to work in up/down mode (counts up until period and then counts back down to zero), the compare match event for CC0 and CC1 can be independently enabled or disabled for either up counting or down counting. This feature is used for asymmetric PWM signal generation.