Version: **
Question: Is there a schematic review checklist for FX2LP™?
Answer: Please check that your hardware meets the following requirements:
- USB data lines: D+/D-
There should be nothing wired on these sensitive high-speed data lines. - There must be pull ups on the SCL and SDA lines.
Recommended values: 2 kΩ -10 kΩ - WAKEUP# pin:
The WAKEUP pin should be in a de-asserted state on power up. The default polarity of the WAKEUP pin is active low. You should have the pin tied high. Do not leave it floating. - RESERVED pin:
Make sure it is grounded directly, as specified in the datasheet. - RESET#:
Make sure the Reset time is adequate and meets the minimum of 5 ms (measured from the time when power ramps up). The max reset time is 100 ms to meet the USB spec. - Crystal:
- The crystal should be according to the following spec:
- 24 MHz ± 100 ppm
- Parallel resonant
- Fundamental mode
- 500 μW drive level
- 12 pF (5 percent tolerance) load cap
- One of the recommended parts is Ecliptek: EC-12-24.000M.
- Make sure that the VCC ramp-up rate meets what is specified in the datasheet. The input must turn on to a valid voltage (3.0 V to 3.6 V) over a 200 μs period. This equates to an 18 V-per-millisecond ramp-up rate. Powering up the input too quickly will latch the internal regulator and cause problems powering up the core. Many 3.3 V regulators have turn-on times that are long enough to properly power up the internal regulator. One such regulator is the LT1763CS8-3.3.
For FX2LP hardware design, please refer to the application note AN15456 - Guide to a Successful EZ-USB® FX2LP™ Hardware Design.
