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Runtime Clock Configuration for PSoC 4 Devices - KBA233007
The IMO is PSoC 4’s main clock source, which clocks the peripherals and the CPU. However, it is also possible to use an external clock (EXTCLK) that is provided to a designated PSoC 4 pin. The HFCLK can be selected from IMO or the external clock. The SYSCLK is an integer division of the HFCLK. The SYSCLK is provided to the Cortex-M0 CPU.
The following diagram shows the clock tree structure for PSoC 4.
Figure 1: PSoC 4 Clock Tree
Note: This KBA does not discuss low-frequency clocks.
When creating a project, the user may require a dynamic change in clock frequency. The following set of APIs can be used to change the clock frequency during runtime:
Changing the IMO frequency dynamically:
/* Setting Flash wait cycles and IMO frequency */ CySysFlashSetWaitCycle(CLK_IMO_MHZ / CY_SYS_CLK_SYSCLK_DIVx); CySysClkWriteImoFreq(CLK_IMO_MHZ);
Note: If the CPU clock frequency increases during device operation, the number of clock cycles that the cache will wait before sampling data comes back from flash should be adjusted. It is not mandatory to set the flash wait cycles when decreasing the clock frequency, but it is recommended to do so to improve CPU performance. The CySysFlashSetWaitCycle() function should be provided with the SYSCLK frequency of operation. SYSCLK = IMO frequency/SYSCLK divider when IMO is the main clock.
Here, CLK_IMO_MHZ is the desired IMO clock frequency. The valid range for this parameter will depend on the specific PSoC 4 device family.
Note: In the CY_SYS_CLK_SYSCLK_DIVx parameter ‘x’ can be equal to 2, 4, 8…,128 and corresponds to the integer by which the HFCLK should be divided to get the desired SYSCLK.
Changing the HFCLK clock source dynamically:
/* Set HFCLK source */ CySysFlashSetWaitCycles(CLK_IMO_MHZ / CY_SYS_CLK_SYSCLK_DIVx); CySysClkWriteHfclkDirect(CY_SYS_CLK_HFCLK_IMO);
Note: Here, the CySysClkWriteHfclkDirect() function is used to select the HFCLK source (such as IMO and EXTCLK).
Changing the SYSCLK frequency dynamically:
/* Set SYSCLK divider */ CySysFlashSetWaitCycles(CLK_IMO_MHZ / CY_SYS_CLK_SYSCLK_DIVx ); CySysClkWriteSysclkDiv(CY_SYS_CLK_SYSCLK_DIVx);