cancel
Showing results for 
Search instead for 
Did you mean: 

Knowledge Base Articles

Route Non-Dedicated Pins as SAR ADC Inputs through AMUXBUSA/B for PSoC 6 MCU in MTB 2.0 – KBA229989

Employee

Route Non-Dedicated Pins as SAR ADC Inputs through AMUXBUSA/B for PSoC 6 MCU in MTB 2.0 – KBA229989

Author: ShipingW_81           Version: **

Translation - Japanese: MTB 2.0 で PSoC 6 MUC の AMUXBUSA/B を経由して専用ピン以外のピンを SAR ADC の入力に接続する - KBA229989 - Community Translate...

In the Device Configurator GUI of MTB 2.0, only dedicated pins (Port10) are available for PSoC 6 SAR ADC inputs. This is because the feature that allows SAR connection to on-chip resources automatically is still not available in MTB 2.0. To connect non-dedicated pins to SAR inputs, the user must manually add code in firmware and connect them through AMUXBUSA/B.

An example of connecting pin 2 and pin 4 of Port1 to three different input channels of SAR ADC is shown in the following figure.

pastedImage_0.png

#define CHANNEL_EN           7u

#define CHANNEL_0_CONFIG    ((uint32_t)CY_SAR_CHAN_SINGLE_ENDED           /* Single-ended channel. */\

                            | (uint32_t)CY_SAR_CHAN_SAMPLE_TIME_1         /* Use Sample Time 1 for 1 us acquisition time. */ \

                            | (uint32_t)CY_SAR_POS_PORT_ADDR_SARMUX_VIRT /* Set the Vplus port address to SARMUX_VIRT for the AMUXBUSA/B.*/\

                            | (uint32_t)CY_SAR_CHAN_POS_PIN_ADDR_2)       /* Set pin address to 2 for AMUXBUSA. */

#define CHANNEL_1_CONFIG    ((uint32_t)CY_SAR_CHAN_SINGLE_ENDED           /* Single-ended channel. */\

                            | (uint32_t)CY_SAR_CHAN_SAMPLE_TIME_1 /* Use Sample Time 1 for 1 us acquisition time. */ \

                            | (uint32_t)CY_SAR_POS_PORT_ADDR_SARMUX_VIRT  /* Set the Vplus port address to SARMUX_VIRT for the AMUXBUSA/B.*/\

                            | (uint32_t)CY_SAR_CHAN_POS_PIN_ADDR_3)       /* Set pin address to 3 for AMUXBUSB. */

#define CHANNEL_2_CONFIG ((uint32_t)CY_SAR_CHAN_DIFFERENTIAL_PAIRED    /* Differential paired channel. */\

                         | (uint32_t)CY_SAR_CHAN_SAMPLE_TIME_1 /* Use Sample Time 1 for 1 us acquisition time. */ \

                         | (uint32_t)CY_SAR_POS_PORT_ADDR_SARMUX_VIRT  /* Set the Vplus port address to SARMUX_VIRT for the AMUXBUSA/B.*/\

                         | (uint32_t)CY_SAR_CHAN_POS_PIN_ADDR_2)       /* Use AMUXBUSA (pin address 2) for Vplus and AMXBUSB (pin address

3)for Vminus. Note, differential input pair. */

#define CHANNEL_CONFIG      {(uint32_t)CHANNEL_0_CONFIG \

,(uint32_t)CHANNEL_1_CONFIG \

,(uint32_t)CHANNEL_2_CONFIG \

,0uL,0uL,0uL,0uL,0uL,0uL,0uL,0uL,0uL,0uL,0uL,0uL,0uL} /* Channels 3 through 15 are unconfigured. */

#define MUX_SWITCH          CY_SAR_MUX_FW_AMUXBUSA_VPLUS        /* Close switch between Vplus and AMUXBUSA for Channels 0 and 2. */ \

                            | CY_SAR_MUX_FW_AMUXBUSB_VPLUS      /* Close switch between Vplus and AMUXBUSB for Channel 1. */\

                            | CY_SAR_MUX_FW_AMUXBUSB_VMINUS     /* Close switch between Vminus and AMUXMBUSB for Channel 2. */ \

                            | CY_SAR_MUX_FW_VSSA_VMINUS)        /* Close switch between Vminus and VSSA for single-ended Channels 0 and 1. */

#define MUX_SWITCH_SQ_CTRL  (CY_SAR_MUX_SQ_CTRL_AMUXBUSA        /* Enable SARSEQ control of AMUXBUSA switch. */ \
                            | CY_SAR_MUX_SQ_CTRL_AMUXBUSB       /* Enable SARSEQ control of AMUXBUSB switch. */ \
                            | CY_SAR_MUX_SQ_CTRL_VSSA)          /* Enable SARSEQ control of VSSA switch. */

  

Cy_GPIO_SetHSIOM(GPIO_PRT1, 2u, P1_2_AMUXA);    /* Connect P1_2 to AMUXBUSA. */

Cy_GPIO_SetHSIOM(GPIO_PRT1, 4u, P1_4_AMUXB);    /* Connect P1_4 to AMUXBUSB. */

/* Set drive mode of P1_2 and P1_4 to analog high-z. */

Cy_GPIO_SetDrivemode(GPIO_PRT1, 2u, CY_GPIO_DM_ANALOG);

Cy_GPIO_SetDrivemode(GPIO_PRT1, 4u, CY_GPIO_DM_ANALOG);

/* To connect the SARMUX to Port 1 requires additional HSIOM switches, AMUX_SPLIT_CTL[1] and AMUX_SPLIT_CTL[6].

  * See the device TRM about AMUXBUS splitting. */

  HSIOM->AMUX_SPLIT_CTL[1] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk \

                             | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk \

                             | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk \

                             | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;

  HSIOM->AMUX_SPLIT_CTL[6] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk \

                             | HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk \

                             | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk \

                             | HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;

Notes:

  • The following table shows the required POS_PORT_ADDR and POS_PIN_ADDR settings for different input connections. The specific POS_PORT_ADDR and POS_PIN_ADDR are used in the above code snippet to connect between SARMUX and AMUXBUSA/B.

Input Connection Selection

POS_PORT_ADDR

POS_PIN_ADDR

SARMUX dedicated port

CY_SAR_POS_PORT_ADDR_SARMUX

CY_SAR_CHAN_POS_PIN_ADDR_0 through CY_SAR_CHAN_POS_PIN_ADDR_7

DieTemp sensor

CY_SAR_POS_PORT_ADDR_SARMUX_VIRT

CY_SAR_CHAN_POS_PIN_ADDR_0

AMUXBUSA

CY_SAR_POS_PORT_ADDR_SARMUX_VIRT

CY_SAR_CHAN_POS_PIN_ADDR_2

AMUXBUSB

CY_SAR_POS_PORT_ADDR_SARMUX_VIRT

CY_SAR_CHAN_POS_PIN_ADDR_3

CTB0 Opamp0 1x output

CY_SAR_POS_PORT_ADDR_CTB0

CY_SAR_CHAN_POS_PIN_ADDR_2

CTB0 Opamp1 1x output

CY_SAR_POS_PORT_ADDR_CTB0

CY_SAR_CHAN_POS_PIN_ADDR_3

  • The AMUX_SPLIT_CTL registers must be used correctly to split the AMUXBUS for connecting different pins. In the above code snippet, AMUX_SPLIT_CTL[1] and AMUX_SPLIT_CTL[6] are used for pin 2 and pin 4 of Port1.

    The specific registers are not described in detail in the device Registers TRM; however,  can be confirmed in the Device Configurator ® Analog-Routing GUI in MTB 2.0. To do this, make sure the shortest path of AMUXBUSA/B is between the target pins and SAR ADC. Navigate the mouse to the switch nodes on the path; the specific node number appears.

pastedImage_25.png

The switch nodes on the path for pin 2 and pin 4 of Port0 are highlighted in red in the above capture. The specific notes are:
amuxt1_aa_sr / amuxt1_aa_sl / amuxt1_bb_sr / amuxt1_bb_sl / amuxt6_aa_sr / amuxt6_aa_sl / amuxt6_bb_sr / amuxt6_bb_sl

You can set the corresponding bits of AMUX_SPLIT_CTL[1] and AMUX_SPLIT_CTL[6] similar to the code snippet.

0 Likes
Version history
Revision #:
1 of 1
Last update:
‎Apr 13, 2020 09:29 PM
Updated by:
 
Contributors