Question: What register should the external master address in order to read the contents of the Interrupt Status Byte?
Answer:
The Interrupt Status Byte is not a register having a fixed address. The SX2 provides an output signal that indicates to the external master that the SX2 has an interrupt condition. When an interrupt occurs, the INT# pin is asserted, and the corresponding bit is set in the Interrupt Status Byte and the Interrupt Status Byte will be available on the lower portion of the data bus (FD [7:0]). The external master can read the Interrupt Status Byte by strobing SLRD/SLOE. Reading the Interrupt Status Byte automatically clears the interrupt. Only one interrupt request occurs at a time; the SX2 buffers multiple pending interrupts. The external master has to read the Interrupt Status Byte only when the interrupt occurs and the data that is available on the data bus (FD [7:0]) just after the interrupt occurs till it is read is the Interrupt Status Byte.
