Question: - Is the address pointer incremented when REN1 & REN2 are asserted, RCLK is toggled, but OE is not asserted? - What happens if RCLK is toggled, but only REN1 is asserted (REN2 is not)?
Answer: In this family of synchronous FIFO's (which includes CY7C4201, CY7C4211, CY7C4221, CY7C4231, CY7C4241, CY7C4251, CY7C4261, CY7C4271, CY7C4281, and CY7C4291), the following conditions must be met for a valid read operation:
- Read Enable 1 (/REN1) and Read Enable 2 (/REN2) must be asserted (LOW)
- Read Clock (RCLK) must be active
- Empty Flag (/EF) must be disabled (HIGH)
- Output Enable (/OE) must be asserted (LOW)
If all four of these conditions are met, the first word in the FIFO will be driven onto the output data bus (Q0-Q8) tA after the rising edge of RCLK, and the read pointer will move to the next location.
If only one of the two Read Enable signals is asserted, the read operation is completely ignored, and the pointer does not move.
If there is no rising edge of RCLK, the read operation is ignored.
If the Empty Flag is asserted, the read operation is ignored.
However, if the first 3 conditions are met, and the Output Enable is disabled (high), the read operation is valid. /OE only controls the output data bus, so if /OE is high, nothing will be driven on Q0-Q8. However, the read operation is indeed valid, so the read pointer will move to the next location.
