Version: **
Question:
What is read access latency for S25FL-S, S25FS-S, and S25FL-L SPI flash memory and how can it be configured?
Answer:
Read commands should have zero to eight dummy cycles inserted into the command sequence to give the flash device enough time to perform the first flash access before the data bytes are transferred from the flash to the host. The register settings for configuring this portion of the read command sequence are called latency codes, and they define how many mode cycles and dummy cycles are required for each read command as the serial clock frequency increases.
Not all read commands have mode bits or dummy cycles; for example the Read 03h command for the S25FL-S:
Some commands have only dummy cycles and no mode cycles; for example the FAST_READ 0Bh command for the S25FL-S:
And other commands have both mode cycles and dummy cycles; for example the Quad I/O Read QIOR EBh for the S25FL-S:
See the S25FL-S, S25FS-S or S25FL-L datasheets for more information about mode bits and how they can save command cycles while performing random access reads. Note that the mode bits are defined in the latency code tables for the S25FL-S family, while the mode bits for the S25FS-S and S25FL-L are defined separately for each command that uses them.
The following three sections reproduce latency code tables from certain density subsets of the S25FL-S, S25FS-S, and S25FL-L family datasheets. It is important that the flash latency code settings and the corresponding settings in the host SPI controller are synchronized to enable correct system operation. If they are not synchronized between the flash and the host, the read output will be shifted by the difference in the number of mode and dummy bits expected by the flash device and host SPI controller (typically a onebyte, two-byte, or four-byte shift).
Latency Codes for S25FL128S and S25FL256S (from Document Number 001-98282, Rev. *J): The Configuration Register 1 bits CR1[7:6] select the 2-bit latency code. A user needs to find proper mode or dummy cycles according to the maximum SPI clock frequency. Note that when a dash “-“ is shown in the table, it means that the read command is not supported at the SPI clock frequency listed in that row of the table.
Latency Codes for S25FS512S (from Document Number 002-00489, Rev. *F): The Configuration Register 2 nonvolatile bits CR2NV[3:0] or volatile bits CR2V[3:0] select the 4-bit Read Latency. A user needs find the proper dummy cycle count (latency cycles) according to the SPI clock frequency. Simply identify one of the sixteen latency cycle counts from the table and write that value to the CR2x[3:0] bits.
Notes:
- “N/A” instead of a SPI clock frequency means that the latency cycle count for that row is not supported by that command.
- The default latency cycle count is '8'.
- Mode cycles are defined by the command, so they are independent of the latency cycles
Latency Codes for S25FL128L and S25FL256L (from Document Number 002-00124, Rev. *C): The Configuration Register 3 nonvolatile bits CR3NV[3:0] or volatile bits CR3V[3:0] select the latency code. A user needs find the proper dummy cycle count (latency code) according to the SPI clock frequency. Simply identify one of the sixteen latency cycle codes from the table and write that value to the CR2x[3:0] bits.
Notes:
- The default latency code is '8'.
- Mode cycles are defined by the command, so they are independent of the latency cycles
