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Protecting a Portion of S25FS512S Main Memory Array and Using it as ‘READ-Only’ - KBA232840

ArunKumarChoul
Employee

Protecting a Portion of S25FS512S Main Memory Array and Using it as ‘READ-Only’ - KBA232840

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Question:
How can a portion of the main memory array (256Mb) of S25FS512S be protected and used as ‘read-only’?

 Answer:
A combination of the Status Register-1 nonvolatile bits BP2, BP1, BP0 (SR1NV[4:2]), and the Configuration Register-1 Nonvolatile Bit 5 CR1NV[5] (TBPROT_O) bit can be used to protect an address range of the main memory array from program and erase operations. The size of the range is determined by the value of the BP bits and the upper or lower starting point of the range is selected by the TBPROT_O bit.  To illustrate the implementation of a protection scheme on a portion of the main memory array, protecting the lower portion (256 Mb) of the main memory array will be used as the example. 

Status Register-1 Nonvolatile bits SR1NV[4:2] (BP_NV2, BP_NV1, BP_NV0):
These bits define the main flash array area to be software-protected against program and erase operations. BP bits allow you to optionally protect a portion of the memory array, ranging from 1/64, 1/32, 1/16, and so on, up to the entire memory array. When one or more of the BP bits is set to 1, the relevant memory area is protected from program and erase operations. Following are the settings to protect the lower portion of the main memory array (256 Mb):

  • BP_NV2 = 1
  • BP_NV1 = 1
  • BP_NV0 = 0

Note:  It is important to note that CR1NV[3] (BPNV_O) remains set at “0” (default nonvolatile).  

Table 1. Status Register 1 Nonvolatile (SR1NV)

ArunKumarChoul_0-1618485067015.png

 

CR1NV[3] (BPNV_O): The BP bits are selected as either volatile or nonvolatile, depending on the state of the BP nonvolatile bit (BPNV_O) in the configuration register CR1NV[3].  When CR1NV[3]=0, the nonvolatile version of the BP bits (SR1NV[4:2]), is used to control Block Protection and the Write Register (WRR) command writes SR1NV[4:2] and updates SR1V[4:2] with the same value. When CR1NV[3]=1, the volatile version of the BP bits (SR1V[4:2]), is used to control Block Protection and the WRR command writes SR1V[4:2] and does not affect SR1NV[4:2].  The CR1NV[3] bit (BPNV_O) should remain in the default state, set as “0” = nonvolatile.  Keeping CR1NV[3] set as default “0” = nonvolatile, during Power-On Reset (POR), hardware reset, or software reset, the bit values in SR1NV[4:2] will be copied to SR1V[4:2], as the default value for the SR1V[4:2] volatile bits.  If CR1NV[3] is set at “1” = volatile, SR1V[4:2] volatile (BP 2-0) bits will be set to binary 111 after Power-on-Reset (POR), hardware reset, or software reset. See Table 2 and Table 3.

CR1NV[5] (TBPROT_O): When TBPROT_O is set to a “0” (default value when shipped from Infineon), the Block Protection is defined to start from the top (maximum address) of the array. When TBPROT_O is set to a “1”, the Block Protection is defined to start from the bottom (zero address) of the array. The desired state of TBPROT_O must be selected during the initial configuration of the device during system manufacture; before the first program or erase operation on the main flash array. CR1NV[5] (TBPROT_O) must not be programmed after programming or erasing is done in the main flash array.

 

Table 2. Configuration Register 1 Nonvolatile (CR1NV)

ArunKumarChoul_1-1618485226321.png

 

Table 3. Lower Array Start of Protection (TBPROT_O = 1)

ArunKumarChoul_2-1618485312995.png

 

Summary

With the combination of the Status Register-1 nonvolatile bits BP2, BP1, BP0 (SR1NV[4:2]) and the Configuration Register-1 nonvolatile Bit 5 CR1NV[5] (TBPROT_O) an address range within the main memory array will be protected from program and erase operations.  However, the desired state of TBPROT_O must be selected during the initial configuration of the device during system manufacture, before the first program or erase operation on the main flash array.  CR1NV[5] (TBPROT_O) must not be programmed after programming or erasing is done in the main flash array.  With regards to the CR1NV[3] bit (BPNV_O), it should remain in the default state, set as “0” (nonvolatile), as during POR, hardware reset, or software reset, the bit values in SR1NV[4:2] will be copied, as the default bit values for SR1V[4:2] volatile bits. 

For more details, see the S25FS512S Datasheet.

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‎Apr 15, 2021 04:24 AM
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