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PSoC™ 4 SCB SPI bus timing test - KBA233619

Chelladurai
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PSoC™ 4 SCB SPI bus timing test - KBA233619

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The Motorola SPI protocol has four different modes based on how data is driven and captured on the MOSI and MISO lines. These modes are determined by clock polarity (CPOL) and clock phase (CPHA). Clock polarity determines the value of the SCLK line when not transmitting data. CPOL = '0' indicates that SCLK is '0' when not transmitting data. CPOL = '1' indicates that SCLK is '1' when not transmitting data. Clock phase determines when data is driven and captured. CPHA=0 means sample (capture data) on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. With CPHA=0, the data must be stable for setup time before the first clock cycle.

CY8CKIT-042, PSoC Creator 4.3 (4.3.0.1445) used to test, set SPI Bit order to MSB, send the first 8-bit data 0x01.

Mode 0: CPOL is '0', CPHA is '0':

Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK. Timing in SPI Component is shown in Figure1. The actual operation sequence is shown in Figure 2.

Chelladurai_0-1627276157161.png
 Figure 1. Timing in SPI Component

Chelladurai_2-1627276545431.png
Figure 2. Timing in actual operation

Mode 1; CPOL is '0', CPHA is '1'

Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK. Timing in SPI Component is shown in Figure 3. The actual operation sequence is shown in Figure 4.

Chelladurai_3-1627277082966.png
Figure 3.Timing in SPI Component 

Chelladurai_4-1627277091573.png
Figure 4. Timing in actual operation

Mode 2: CPOL is '1', CPHA is '0'

Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK. Timing in SPI Component is shown in Figure5. The actual operation sequence is shown in Figure 6.

Chelladurai_5-1627277263449.png
Figure 5. Timing in SPI Component

Chelladurai_6-1627277270365.png
Figure 6. Timing in actual operation

 

Mode 3: CPOL is '1', CPHA is '1'

Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK. Timing in SPI Component is shown in Figure7. The actual operation sequence is shown in Figure 8.

Chelladurai_7-1627277396777.png
Figure 7. Timing in SPI Component

Chelladurai_8-1627277404594.png
Figure 8. Timing in actual operation

As a conclusion, when the SPI bus starts to transmit data, the MOSI will be driven before the SS is effective. This design conforms to SPI protocol and can communicate normally.

Here, the MOSI drive mode has been configured to “strong drive” mode during the firmware startup in cyfitter_cfg.c. If the SPI interface is used to simulate other communication protocols, the starting sequence should be taken into consideration.

Reference:

PSoC™ 4100/4200 family PSoC™ 4 architecture TRM


 

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Last update:
‎Jul 25, 2021 11:07 PM
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