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PSoC 4 CapSense Sigma Delta Modulator (CSD) Sequencer - KBA229656


PSoC 4 CapSense Sigma Delta Modulator (CSD) Sequencer - KBA229656

Author: RyanZ_36          Version: **

Translation - Japanese:PSoC 4 CapSense シグマデルタモジュレータ (CSD) シーケンサ - KBA229656- Community Translated (JA)

How does PSoC® 4 CapSense® Sigma Delta Modulator (CSD) hardware work when capacitive sensing operation starts?

CSD sequencer controls the CapSense hardware during the capacitive sensing operation. The CSD sequencer has the following states: Idle, Coarse Initialization, AutoZero, Sample Initialization, and Sample Normal.




In this state, you can configure the CapSense system for capacitive sensing and ADC measurements by writing to the CapSense registers.

Coarse Initialization

This state is intended for CMOD capacitors coarse initialization before the beginning of sensor scan. In the coarse initialization state, the voltage on CMOD is initialized to VREF. During this state, internal switch connects VDDA to CMOD. Comparator opens the switch when the voltage on CMOD reaches Vref.


In the autozero state, the CSDCOMP and HSCOMP comparators will be auto-zeroed to reduce the input offset voltage. By default, AutoZero is configured as skipped.

Sample Initialization

In this state, the CSD sequencer performs dummy sensor scan to initialize the CMOD voltage accurately to Vref. The CMOD capacitor is approximately initialized to Vref during the coarse initialization phase and accurately initialized to Vref during the sample initialization phase. When the CSD sequencer enters the sample initialization state, it alternately connects CS capacitor to AMUXBUSA and to ground. This action causes the voltage on CMOD capacitor to go below Vref and the CSDCOMP trips. When CSDCOMP trips, IDAC is enabled to charge the CMOD back to VREF. This process is repeated for a certain duration. By default, the duration is 10 sense clock cycles. There are several microseconds gap time for reconfiguring CSD before sample initialization and after coarse initialization.

Sample Normal

The sample normal state is similar to the sample initialization state except that the firmware reads the counter result at the end of scanning to detect finger touch.

Note: Coarse initialization uses the connection between VDDA and CMOD, instead of IDAC, to speed up charging CMOD to Vref.

For more details, visit Cypress community or contact Cypress sales team.

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‎Feb 18, 2020 11:05 PM
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