PLL0 Clock Down Test of Clock Supervisor in Traveo S6J3XXX Series MCUs - KBA222351
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Version: *A
Translation - Japanese: Traveo S6J3XXXシリーズMCUのクロック監視のPLL0クロックダウンテスト - KBA222351 - Community Translated (JA)
Question:
In the PLL0 clock down test of clock supervisor in Traveo S6J3XXX series MCUs, CPU is not reset when a CSV error of PLL0 occurs. How can I reset the CPU when a CSV error of PLL0 occurs?
Answer:
According to the recommended clock settings of the target products, CPU cannot be reset when a CSV error of PLL0 occurs.
When a CSV error of PLL0 occurs, NMI (IRC0_NMIVA5) is notified to the CPU.
The following figure shows the behavior of reset or NMI when CSV error of PLL0 occurs.
For the target products, select SSCG0 for clock domain 0 or MCUC clock distribution. Note that PLLm cannot be selected.
Therefore, when a CSV error of PLL0 occurs, the CPU is not reset and NMI is notified for the target products.
Note: This KBA applies to the following series of Traveo MCUs:
S6J3300
S6J3350
S6J3360
S6J3370
S6J3400
S6J3510
- Tags:
- auto mcu
- clock supervisor
- s6j3
- s6j3300
- s6j3310
- s6j3320
- s6j3330
- s6j3340
- s6j3350
- s6j3360
- s6j3370
- s6j3400
- s6j3510
- traveo