PLL Clock Jitter Impact on CAN Precision in Auto MCU – KBA222406

[Community-Team]

Version: **

Translation - Japanese: PLLクロックジッターの車載向けMCU CAN精度に対する影響 – KBA222406

Question:

When PLL clock used for a CAN peripheral, how do I verify whether the PLL clock jitter meets the CAN precision specification?

Answer:

Use the following equation to evaluate the impact of PLL Jitter on CAN precision:

df_jitter = t_jitter / (10×NBT),

where t_jitter is the specified PLL clock jitter as the absolute interval ( CAN PLL Jitter provided in product datasheet) and NBT is the Nominal Bit Time (the inverse of a given CAN bit rate). The result of  df_jitter is the drift equivalent and should be added to the oscillator drift value of the crystal or resonator:

df_total = df_jitter + df_oscillator .

Here is an example to check whether the PLL clock of S6J3120 meets the CAN precision specification.

Example:

CAN bus bit rate = 500 kbps,

CAN PLL Jitter = ±10ns  (t_PJ from AC Characteristics of the S6J3120 series datasheet),

Oscillator drift of external crystal  df_oscillator = ±0.01% (generally provided by the crystal supplier),

Allowed CAN node frequency tolerance   df   = ±0.3%.

The relative PLL Jitter interval ±10 ns results in an absolute intervalt_jitter = 20_ns. The 500 kbps bit rate results in NBT = (1/500 kbps) = 2 µs.

  df_jitter= 20_ns / 10×2_us = ±0.1%,

  df_total = 0.1% + 0.01% = ±0.11% < df  = ±0.3%,

Therefore, the CAN PLL Jitter spec of S6J3120 meets the CAN specification.

[HongyanW_86]

df_jitter = t_jitter /(10xNBT)