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NOP cycles in Sync SRAMs

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NOP cycles in Sync SRAMs

Question: When is a second NOP cycle required in Sync SRAM?



  A NOP cycle (a memory cycle where neither a read or write operation is performed) is required in some SRAM designs where the data input and output share the same pin.  It is needed to provide time to turn around a bidirectional data bus direction.

Sync NoBL SRAMs do not require any NOP cycles as they are designed to turn the bidirectional data bus around within one clock cycle.

DDRII/II+ SIO (Separate IO) devices and all QDRII/II+ devices also do not require any NOP cycles because the data input and output are on separate pins.  With these devices data busses are all unidirectional and do not turn around.

Only DDRII/II+ CIO (Common IO) devices have bidirectional data busses that require at least one NOP cycle to turn the data bus around.  In some cases, these devices may require a second NOP cycle between a read and write cycle.

Please refer timing diagram below.


Here, two NOP cycles are inserted in cycles 4 and 5 to allow the data bus to transition from a read to a write operation in cycle 6.  Looking at the DQ pin timing, the Read cycle started in cycle 3 finishes driving the read data in cycle 5.  The Write cycle started in cycle 6 expects data to be driven on the data bus in cycle 7.  That leaves cycle 6 idle on the data bus which allows time for the data bus to turn around.

Note that a NOP cycle is not needed to transition the data bus from a write to read direction because the internal read latency of the SRAM will provide enough delay to turn the bus around.

One NOP cycle or Two?

What if the two NOP cycles in the above example were reduced to only one NOP cycle?  In this case, the Write cycle would instead start in cycle 5 and expect data to be driven on the data bus in cycle 6.  This is the next data bus cycle after the Read cycle finished.  There would be no idle cycle for bus turn around time here.

This would be acceptable if the following timing conditions can be met by the memory controller design.  The total of Tchz (clock rise to high-Z) and Tsd (data setup to clock rise) must be less than ½ of Tcyc (clock cycle period).  The reason only ½ Tcyc is allowed is because the data is transitioning at every clock edge.

Tchz + Tsd  <  ½ Tcyc

If the above condition is met for all process, voltage, and temperature variations, then one NOP cycle will work.  It can be easily seen that as the frequency of the design increases, a second NOP becomes necessary.  Most high speed designs will require two NOP cycles.

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