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Will the Data Learning Pattern (DLP) be enabled when the number of dummy cycles is less than 5?
Cypress serial NOR flash devices have an optional data learning pattern (DLP) feature for DDR read operations to help the memory controller to more accurately center the data capture point for the received data bits.
The DLP feature is enabled by writing any data other than 0x00 into DLP registers (VDLR or NVDLR). When programming NVDLR, a copy of the data pattern in NVDLR will also be written to VDLR (Note: NVDLR is a One-Time-Programmable register. Once programmed, NVDLR cannot be reprogrammed or erased). VDLR can be written to at any time, but on reset or power cycle, the data pattern will revert back to what is in NVDLR.
If the DLP feature is enabled, the flash device will output the Data Learning Pattern present in VDLR register for 4 clock cycles immediately before the data is output. At least one more dummy cycle before DLP output is required to allow additional time for the host to stop driving I/O signals before the flash device starts driving, to minimize I/O driver conflict. So, the minimum number of dummy cycles required for a DDR read operation to use DLP feature is 5. The host should not drive the I/O signals during dummy cycles .
If the number of dummy cycles configured is less than 5, the flash device will work as if the DLP feature is disabled. The flash device will output data after the configured number of dummy cycles.
For example, see the waveform below for DDR Dual I/O read operation with DLP enabled: the number of dummy cycles configured is ‘5’ for S25FL256S serial NOR flash device. DLP registers are programmed to 0x34.