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Question: When using the CY2308 zero delay buffer, does it generate any jitter of its own at the output with respect to its input?
The CY2308 is PLL based zero delay clock buffer. The jitter transfer characteristic is that of second order low-pass filter with the -3dB point at approximately 1MHz (also called close loop bandwidth). This means that if the jitter frequency is less than loop bandwidth, it will pass through the PLL and appear on all outputs. Otherwise, the filter will attenuate the jitter at the rate 20dB per decade. The cycle-to-cycle jitter of REF is a really high frequency, and it will be greatly attenuated. The primary causes of cycle-to-cycle jitter for the output is power supply noise on PLL's supply inputs and the random thermal mechanical noise.