Internal Routing of RESET# Signal on S71KL-S HyperFlash™/HyperRAM™ MultiChip Package (MCP) - KBA219070

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JP Translation:S71KL-S HyperFlash™/HyperRAM™ マルチチップパッケージ(MCP)のRESET#信号の内部配線 - KBA219070

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Question:

Why is the RESET# signal not connected to the HyperRAM die in the S71KL-S HyperFlash/HyperRAM Multi-Chip package?

Answer:

In addition to resetting the flash, the RESET# signal on ball A4 is used on the HyperFlash die to enter a special test mode by putting a high voltage on that signal. The high voltage is not compatible with the HyperRAM die, so both RESET# signals cannot be connected to ball A4.

The RESET# signal can be used on the discrete HyperRAM chip to do the following:

• Return the device to the standby state
• Cause the configuration registers to return to their default values
• Halt the self-refresh operation while RESET# is LOW
• Force the device to exit the Deep Power Down state

To achieve the same results on the HyperRAM die that is part of the S71KL-S HyperFlash/HyperRAM MCP, the user must trigger a full power-on reset (POR) for the MCP. This is done by ensuring that when V_CC drops below V_LKO = 2.7 V that V_CC then drops below V_RST = 0.7 V for at least t_PD = 50 µs before rising past V_CC(MIN) = 2.7 V to the nominal operating range of 2.7 V–3.6 V. Note that the first access to the MCP should happen after t_VCS = 300 µs elapses from the time V_CC passes V_CC(MIN).                                                                                                                 

	HyperFlash	HyperRAM
VCC	2.7 V–3.6 V	2.7 V–3.6V
VLKO	2.7 V min	2.4 V min
VRST	0.8 V min	0.7 V min
tPD	50 µs min	10 µs min
tVCS	300 µs max	150 µs max