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How do I use a 3.3-V device (for e.g., 3.3 V character LCD) with a 5-V powered PSoC® 3/ PSoC® 5LP
In PSoC® 3/5LP, I/Os are divided into four quadrants. The pins VDDIO0, VDDIO1, VDDIO2, and VDDIO3 are used to power the I/Os of each quadrant respectively. Therefore, each quadrant can operate their I/Os at logic voltage levels different from the other quadrants. This means that even if the device is operating at 5 V, one or more quadrants can be configured for 3.3 V logic levels, thereby the I/Os in the quadrant/s can be interfaced with an external device operating at 3.3 V.
The VDDIO pins should be supplied with a reference voltage to control the I/O logic voltage levels. In PSoC 3/5LP, this reference voltage can be generated inside the chip itself. A voltage DAC (VDAC) can be used to generate the required reference voltage. The VDAC output is fed to an opamp buffer to increase the drive strength (25 mA source/sink for the entire quadrant). The output of the opamp must be connected to VDDIOx externally.
The advantage of this method is that the voltage DAC provides 8 bits of programmability to the reference voltage. This means that the logic voltage levels of I/Os can be varied during runtime if required.
Figure 1 shows the required connections:
The diagram above shows how to operate Quadrant 0 at a different I/O logic voltage level (through VDDIO0). The opamp output is routed to P3, which belongs to Quadrant 3. Quadrant 3 will be powered by the device voltage (VDD = 5V, by leaving pin VDDIO3 open). The blue line shown above implies an external wire connection.
Figure 2 shows the configuration of the DAC and op-amp to generate 3.3 V.