I/O Switching Power for Sync SRAM

[Anonymous]

Is the IDD (VDD operating supply current) current specified in the sync SRAM datasheets sum of both the core current and I/O current?

No. The current specified in the datasheets indicate just the current consumption by the core of the memory (I_DD). The current drawn by the I/Os (I_DDQ) is not specified in the datasheets as this value depends on the load driven by the I/O’s of the device and the number of I/O’s switching. Please use the power calculator tool in the following link to calculate the I/O switching power for sync SRAM products.

For example, let us consider a QDR-II memory (for example, CY7C1315KV18 - Density 512 K x 36)

1. Activity factor ‘α’ =1 (Because the data gets transferred on both edges of the clock, 0.5 for Standard Sync and NoBL)
2. Maximum Clock Frequency ‘f’ is 333 MHz
3. Load Capacitance C_L is 5 pF (This value depends on the actual board layout and the load capacitance seen by the output pin of the memory)
4. Number of Switching I/Os N is 36 (This will be the number of I/Os driving the load)
5. V_DDQ is 1.9 V maximum
     Based on the formula, P = α f C_L V_DDQ² N
     I/O Switching Power is 216 mW
     I_DDQ is 113 mA

Customers must use this to design their power circuitry accordingly.