Question: Why Synopsys VCS gives incorrect simulation result with QDR-DDR II/II+/Xtreme verilog models?
Answer: Cypress provides verilog model for each product after verifying them using Altera Modelsim. Other verilog simulators like Xilinx ISE and Mentor Graphics Questa can also simulate these verilog models with correct outcome.
Problem statement: QDR-DDR II/II+/Xtreme verilog models give erroneous simulation results with Synopsys VCS while other simulators like Altera Modelsim, Xilinx ISE, and Mentor Graphics Questa do not produce the same errors.
Below is the simulation result for verilog model using Altera Modelsim.
............ (e.g. CY7C2564XV18)
.......................
# Line: 12 OUTPUT DATA OK data = 06038180e test = 06038180e
# Line: 13 OUTPUT DATA OK data = 04028100a test = 04028100a
# Line: 14 OUTPUT DATA OK data = zzzzzzzzz test = zzzzzzzzz
# Line: 15 OUTPUT DATA OK data = zzzzzzzzz test = zzzzzzzzz
# Line: 16 OUTPUT DATA OK data = 0884c2213 test = 0884c2213
# Line: 17 OUTPUT DATA OK data = 0683c1a0f test = 0683c1a0f
# Line: 18 OUTPUT DATA OK data = 0b0602c18 test = 0b0602c18
# Line: 19 OUTPUT DATA OK data = 090502414 test = 090502414
# Line: 20 OUTPUT DATA OK data = 0d874361d test = 0d874361d
# Line: 21 OUTPUT DATA OK data = 0b8642e19 test = 0b8642e19
.......................
Below is the simulation result for the same verilog model using Synopsys VCS.
....... .. (e.g. CY7C2564XV18)
....................
Line: 12 OUTPUT DATA OK data = 06038180e test = 06038180e
Line: 13 ERROR data = zzzzzzzzz test = 04028100a
Line: 14 OUTPUT DATA OK data = zzzzzzzzz test = zzzzzzzzz
Line: 15 OUTPUT DATA OK data = zzzzzzzzz test = zzzzzzzzz
Line: 16 OUTPUT DATA OK data = 0884c2213 test = 0884c2213
Line: 17 ERROR data = zzzzzzzzz test = 0683c1a0f
Line: 18 OUTPUT DATA OK data = 0b0602c18 test = 0b0602c18
Line: 19 ERROR data = zzzzzzzzz test = 090502414
Line: 20 OUTPUT DATA OK data = 0d874361d test = 0d874361d
Line: 21 ERROR data = zzzzzzzzz test = 0b8642e19
.....................................................................
……………
Explanation for the errors:
VCS simulation result shows some erroneous output from the same verilog model. The reason for this is that, the reg Data_out is been driven by two drivers at the same time, as shown in the verilog code snippet,
`define tcqd #0.15
`define tcqdoh #0.15
reg [35:0] Data_out;
......
always @(datahold_clk)
begin
if(chip_oe == 1) `tcqdoh Data_out = 36'bz;
end
...
always @(posedge echo_clk)
begin
if (rpen_o_o_o_o == 0)
Data_out = `tcqd mem2[Read_Address_o_o_o_o];
end
always @(posedge echo_clkb)
begin
if (rpen_o_o_o == 0)
Data_out = `tcqd mem1[Read_Address_o_o_o];
end
...
always @(datahold_clk)
begin
if(tristate == 0) `tcqdoh Data_out = 36'bz;
end
Here all clk events happen at same time and the drivers are writing Data_out after 0.15 ns delay (tcqd and tcqdoh), causing nondeterminism in the model. The simulator takes the liberty of executing the statements in different processes in different order. This nondeterminism in event ordering is random and different HDL simulators may behave differently in terms or resolving these or behave same.
Resolution of error:
To actually resolve this, we need to make sure the driving events are not happening at the same time in non-blocking assignment statements. Change the delay "tcqdoh" to 0.14 or a value slightly less than 0.15. This will make a VCS simulator to know the defined order of event execution.
