Strictly necessary cookies are on by default and cannot be turned off. Functional, Performance and Tracking/targeting/sharing cookies can be turned on below based on your preferences (this banner will remain available for you to accept cookies). You may change your cookie settings by deleting cookies from your browser. Then this banner will appear again. You can learn more details about cookies HERE.
Strictly necessary (always on)
Functional, Performance and Tracking/targeting/sharing (default off)
Theseinstructions forreading the ECC enable/disable status for each 16B ECC page are based on the HyperFlash™ datasheet: 001-99198 Rev. *M.
The 2B ECC Status Register (ECCSR) contains one bit ECCSR=ECCD1 that tells whether the ECC logic is turned on for a given 16B ECC page.
If ECCD1 = ‘0’, ECC is enabled for the 16B half page, and probably no more than one program operation has been applied to that half page since the last erase.
If ECCD1=’1’, ECC is disabled for the 16B half page, and more than one program operation has been applied to that half page since the last erase.
In other words, if ECC is disabled, we know that multi-pass programming happened on that half-page. Otherwise, if ECC is enabled, then single-pass programming may have happened on that half-page.
To read the ECCSR, you need to enter the ECC Status ASO (address space overlay). There is an ASO entry command, and an ASO Exit command (A.K.A. software reset).
Here are the ECC ASO Entry and Exit commands:
Once the flash has entered the ECC ASO state, all reads at a given address return the ECCSR value for the page address that is derived from the word address of the reading location. That is, once in the ECC ASO state, no special command is required to read the ECCSR.
So, RA can be any word address within the 16B=8W aligned ECC page; the hardware automatically masks the address you provide to derive the page address.
Your software does not have to manage any timing delays while performing ECCSR reads – normal HyperBus read timing applies.