Author : HemanthR_06 Version: **
Translation - Japanese: GPIFピンの極性 - KBA224208 - Community Translated (JA)
How do you interpret the polarity of GPIF pins based on the pin configuration chosen in GPIF Designer?
GPIF interface pins of FX3 can be configured as input or output when used as GPIO. The polarity of Input /Output pins can be configured in GPIF II Designer. This article discusses the following three cases:
Figure 1. Output GPIO Active HIGH Polarity
In this configuration (see Figure 1), GPIO_17 (with Active HIGH polarity) will be driven HIGH (3.3 V) when it enters the state (READDATA) where DR_GPIO is called. In other states, the GPIO is driven LOW (0 V). See Figure 2 for the state machine.
Figure 2. Output GPIO Example State Machine
b. Output pins (when used as DMA Flags):
A GPIF interface pin can also be configured as a DMA flag and can be configured to have the polarity as Active LOW or HIGH. The drive values will depend on whether it is indicative of a socket taking data into FX3 or out of FX3.
- If the DMARDY flag for a socket which takes data into FX3 is configured as:
-If the DMARDY flag for a socket where data is read out by an external device is configured as:
For example, consider the following flag configuration for FLAGA and FLAGC, taken from application note AN65974 – Designing with the EZ-USB FX3 Slave FIFO Interface:
Case A: Writing data from an external master to FX3
FLAGA is Thread_0_DMA_Ready, which is associated with the socket that takes data from the external master. When the Thread_0_DMA_Ready flag is configured as Active LOW, the flag is driven LOW (0 V) when no buffer is available for the external master to write into PIB_SOCKET_0. When the flag is configured as Active HIGH, it is vice-versa.
Case B: Reading data from FX3 GPIF socket to external master
FLAGC is Thread_3_DMA_Ready, which is associated with the socket that provides data to the external master. When the Thread_3_DMA_Ready flag is configured as Active LOW, the flag is driven LOW (0 V) when no buffer is available for the external master to read from PIB_SOCKET_3. When the flag is configured as Active HIGH, it is vice versa.
However, if the DMA_RDY flag is internally used in the state transition (as shown below), then it should be interpreted as follows:
The DMA_RDY_TH0 variable in the transition from DMAWAIT to READDATA state indicates that the buffer is available for writing. The variable ‘!DMA_RDY_TH0’ indicates that the buffer is not available.
c. Input Pins:
An unused GPIF interface pin configured as input pin. The choice of polarity does not matter for Input pins.
Consider an input ‘VALID’ that is configured as follows:
This input has the following state transition:
Irrespective of the polarity of ‘VALID’ chosen in GPIF II Designer, the above state transition is interpreted as follows: