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Fix “Bad JTAG communication: Write to IR: Expected 0x1, got 0x0 (TAP Command : 2) @ Off 0x5” Error in SEGGER J-Link Debugging Provided with FX3 SDK - KBA229087

ChaitanyaV_61
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Fix “Bad JTAG communication: Write to IR: Expected 0x1, got 0x0 (TAP Command : 2) @ Off 0x5” Error in SEGGER J-Link Debugging Provided with FX3 SDK - KBA229087

Author: KandlaguntaR_36            Version: *A

Translation - Japanese: :FX3 SDKで提供されるSEGGER J-Linkデバッガで“Bad JTAG communication: Write to IR: Expected 0x1, got 0x0 (TAP Com...

Question:
The following error is displayed while debugging Cypress' FX3 USB Super-speed Device Controller using the Segger J-Link debugger

Bad JTAG communication: Write to IR: Expected 0x1, got 0x0 (TAP Command : 2) @ Off 0x5

Why does this happen? How do I fix the error?

Answer:
This error occurs with the FX3 family during JTAG debugging using the Segger J-Link. This is due to change in FX3 CPU frequency during runtime.

In the ROM bootloader mode, the CPU is being set to operate at 96 MHz. In the application firmware, the CyU3PDeviceInit API is used to change the frequency to the desired value. This results in the operating clock frequency being changed at runtime. The typical CPU operating frequency is set to 192 MHz by passing NULL to the CyU3PDeviceInit API.

When the operating clock frequency of the FX3 device changes at runtime, there is a possibility that JTAG debug session using the JLINK debugger might break.

You can prevent this problem by setting up the FX3 device clocks to the desired value during JTAG initialization. If the clocks have already been setup to the desired value, the FX3 API will not make any further changes.

Add the following commands to the Startup tab of Debug Configurations settings to operate the CPU at 192 MHz frequency as shown Figure 1.

# Clock input is 19.2 MHz: Value = 0x00080014

monitor memU32 0xE0052000 = 0x00080014

# Add a delay to let the clock stabilize.

monitor sleep 1000

Figure 1. Startup Tab of Debug Configurations Settings

pastedImage_12.png 

To operate the CPU at highest frequency (403.2 MHz divided by 2) with 19.2 MHz clock, use the following commands:

# Clock input is 19.2 MHz: Value = 0x00080015

monitor memU32 0xE0052000 = 0x00080015

# Add a delay to let the clock stabilize.

monitor sleep 1000

For more details on the 0xE0052000 register (PLL Configuration Register), see the FX3 Technical Reference Manual.

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Last update:
‎Dec 05, 2019 05:08 PM
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