Translation - Japanese: PSoC® 3/4/5LP デバイスとコンパイラのエンディアンフォーマット - KBA91560 - Community Translated (JA)
The PSoC® 3 Keil Compiler uses big endian format for 16- and 32-bit variables. The PSoC 3 device uses little endian format for muti-byte registers (16- and 32-bit registers). How do you swap the order of the bytes while accessing the register through the CPU and DMA? Is this applicable for PSoC 4/5LP devices that use the GNU Compiler Collection (GCC) or Keil™ Microcontroller Development Kit (MDK) compilers?
The Keil Compiler provides macros (defined in cymem.a51) to access registers that internally control byte swapping. These macros must be used to access 8-, 16-, and 32-bit registers in PSoC 3 devices.
Macros for accessing registers mapped in the first 64K of XDATA space:
Macros for accessing registers mapped above the first 64K of XDATA space:
When the source and destination data is organized in different endianness, the DMA transaction descriptor can be programmed to have the bytes endian swapped while in transit.
The SWAP_EN bit of the PHUB.TDMEM[0..127].ORIG_TD0 register specifies whether an endian swap should occur. If SWAP_EN is ‘1’ then an endian swap will occur. The size of the swap is determined by the SWAP_SIZE bit of the PHUB.TDMEM[0..127].ORIG_TD0 register.
CyDmaTdSetConfiguration(myTd, 2, myTd, TD_TERMOUT0_EN | TD_SWAP_EN);
CyDmaTdSetConfiguration(myTd, 4, myTd, TD_TERMOUT0_EN | TD_SWAP_EN | TD_SWAP_SIZE4);
PSoC 4/5LP designs use a GCC or MDK compiler that is based on little endian, unlike the PSoC 3 Keil Compiler. Therefore, DMA byte swapping must be disabled when the code is ported to a PSoC 5LP device. The same is not applicable for PSoC 4 because there is no DMA support for PSoC 4.
PSoC 4 DMA (for PSoC 4 devices that support DMA) architecture is slightly different than PSoC 3/5LP DMA. There is no endian swapping in PSoC 4 DMA. For more details, refer to the PSoC 4 DMA Component Datasheet.