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EZ-PD™ Barrel connector replacement (BCR) FAQs - KBA231336

Chelladurai
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Community Manager

EZ-PD™ Barrel connector replacement (BCR) FAQs - KBA231336

Version: **

EZ-PD™ BCR is Infineon® highly-integrated pre-programmed USB Type-C port controller targeting electronic devices that have legacy barrel connectors (up to 100W) or USB micro-B connectors for power such as drones, smart speakers, power tools, and other rechargeable devices. EZ-PD™ BCR complies with the latest USB Type-C and USB Power Delivery (PD) standards and enables users to quickly convert their devices from being powered through a barrel connector to being powered via the USB-C connector with few external components and no firmware development is required.

This document covers frequently asked questions about the EZ-PD™ BCR product family including the CYPD3176 and CYPD3178 devices.

Question 1: Can I use the same USB-C connector used by the EZ-PD™ BCR chip for syncing power for data communications over USB also? How do I enable USB data capabilities in a BCR application?

Answer: For USB 2.0 based communication, it is possible to use the same connector used for syncing power. For USB 3.0 specific communication, you must use a flip mux that is controlled by the FLIP pin of the BCR device.
Note that the data communications capability bit in the sink capabilities field must be modified by using the appropriate pull-up resistor tied to the FLIP pin. See the latest EZ-PDTM BCR datasheet for more details.

Question 2: Can the VDDD pin of the EZ-PDTM BCR device be used for powering external circuits?

Answer: No, the VDDD pin cannot be used for this purpose. The EZ-PDTM BCR device has a 3.3-V VDDD output (that is derived from the VBUS input using an internal LDO) which is used for the resistor divider network on VBUS_MIN, VBUS_MAX, ISNK_COARSE and ISNK_FINE pins. These resistor divider networks help to determine the corresponding values for the EZ-PDTM BCR chip. This internal LDO cannot source sufficient current to power anything other than these resistor divider networks.

Question 3: Can the default power data object (PDO) selection made by the EZ-PDTM BCR device be modified over the host processor interface (HPI)? If so, does the HPI override of the PDO selection stay through power cycles or does it revert to the default after the power cycle/loss?

Answer: In the CYPD3177 chip, the default PDO selection is controlled by the resistor divider settings for VBUS_MIN, VBUS_MAX, ISNK_COARSE and ISNK_FINE. The default PDO selection can be overridden using HPI commands. However, the HPI override of the PDO selection does not stay through power cycles. Upon each power cycle, default PDO selection will revert to settings determined by the VBUS_MIN, VBUS_MAX, ISNK_COARSE and ISNK_FINE as set by the resistor dividers.

Question 4: How can I measure the VBUS current using the CY4533 EZ-PD™ BCR EVK?

Answer: You can measure the VBUS current on the CY4533 EZ-PD™ BCR EVK by using the CY4500 EZ-PD™ protocol analyzer or any other USB-C inline analyzer. The ideal setup for the connection is to connect the CY4500 EZ-PD™ protocol analyzer as shown in Figure 1. See the CY4500 EZ-PD™ protocol analyzer user guide for more details.

Figure1.PNG

Figure 1. Measurement of VBUS current on CY4533 EZ-PDTM BCR kit using CY4500 EZ-PDTM protocol analyzer

Question 5: What are the changes in the latest version of the EZ-PDTM BCR firmware? How do I find out if the BCR chip I received has the latest firmware?

Answer: See KBA231981 to learn about the changes made to the pre-programmed firmware of the CYPD3177 device. It also lists the date code information used to identify the firmware revision. For CYPD3176 and CYPD3178, there are no firmware revisions yet as of October 2021. Contact the local Infineon® sales representative for updated information.

Question 6: How do I set up the undervoltage lockout threshold of a buck regulator that connects to the DC output of the EZ-PDTM BCR circuit?

Answer: The undervoltage lockout must be set to a value slightly lower than the VBUS_MIN setting.

For example, if the VBUS_MIN is set to 9 V, the EZ-PDTM BCR chip will make power contracts only if the advertised PDOs are 9 V or higher. In this case, the UVLO threshold of the buck regulator that is connected to the DC output of the EZ-PDTM BCR circuit can be set to approximately 8.1 V (10% lower than 9 V).

Question 7: If the power source connected to EZ-PDTM BCR device advertises several PDOs within the VBUS_MIN and VBUS_MAX limits, which PDO will the BCR device select?

Answer: In this scenario, the EZ-PDTM BCR device will select the PDO with the highest voltage rating that is offered within the VBUS_MIN and VBUS_MAX limits.
For example, if VBUS_MIN is 9 V and VBUS_MAX is 15 V, and the offered PDOs are 5 V, 9 V, 15 V, and 20 V, the BCR chip will select 15 V.

Question 8: What are the design considerations for selecting the VBUS_FET? Why do I need a back-to-back pair of FETs for the design?

Answer: The RDS_ON at 5 V will have the highest impact on the thermal performance and efficiency of the design. The RDS_ON along with the thermal resistance of the package will also determine the case temperature (thereby, junction temperature) of the FET. A plateau voltage (VGSPL) of 4 V is recommended. An absolute maximum VGS of 20 V is recommended or a zener diode must be used.
The back-to-back pair of FETs are required mainly to avoid reverse current that will flow in the backward direction from the load to the source. When both the FETs are turned on, the body diodes of both the FETs are arranged in such a way that the current can only flow from the source to the load.

Question 9: What are the design considerations for setting ISNK_FINE and ISNK_COARSE?

Answer: The main consideration for setting ISNK_COARSE and ISNK_FINE values should be such that the sum of currents set by ISNK_COARSE and ISNK_FINE should be equal to or greater than the total current capability of the entire EZ-PDTM BCR circuit.
For example, if the current consumption can be as high as 2 A, the ISNK_COARSE and ISNK_FINE values should be set to at least 5% greater than 2 A (i.e., 2.1 A). However, because the minimum ISNK_FINE increment offered is 250 mA, the sum of ISNK_COARSE and ISNK_FINE currents should be set to 2.25 A.

Question 10: What are the design considerations for setting up the VBUS_MIN and VBUS_MAX values?

Answer: The design considerations for setting up the VBUS_MIN and VBUS_MAX values depend on the power management architecture of the system.
If the DC output of the EZ-PDTM BCR circuit is hooked up to a buck-boost converter that will either buck or boost the DC output from the BCR circuit to the desired system voltage, it is recommended to set VBUS_MIN to 5 V and VBUS_MAX to 20 V. This will offer the most interoperability with commercially available PD adapters.
If the system operates at one of the standard PD voltages (5 V, 9 V, 15 V, or 20 V), a buck-boost converter can be avoided by setting both the VBUS_MIN and VBUS_MAX values to the desired PD voltage. Note that this approach provides much lesser interoperability compared to the previous approach.

Another approach that offers slightly wider interoperability is to use a buck regulator and ensure that VBUS_MIN is set to a voltage greater than the input that can be handled by the buck regulator. See the following examples:

Example 1:
Consider the case where system voltage needed is 6 V. In this scenario, VBUS_MIN can be set to 9 V and VBUS_MAX can be set to 20 V. This can be achieved by interfacing a buck regulator that can provide a 6-V output with a 9-V to 20-V input. However, this system will not be interoperable with USB-C adapters that provide only 5 V output. If this interoperability is desired, it is better to use a buck-boost regulator that can provide a 6-V output with a 5-V to 20-V input and set VBUS_MIN to 5 V and VBUS_MAX to 20 V.

Example 2:
Consider the case where the system voltage needed is 9 V. In this scenario, VBUS_MIN can be set to 9 V and VBUS_MAX can also be set to 9 V. This avoids the need for any DC-DC regulator. However, this system will not be interoperable with USB-C adapters that provide only 5-V output.

Example 3:
Consider the case where the system voltage needed is 24 V. In this scenario, VBUS_MIN can be set to 5 V and VBUS_MAX can also be set to 20 V. One will need to use a boost regulator that can operate from an input of 5 V to 20 V to provide the desired system voltage of 24 V.

Question 11: What if my system requires a non-standard PD voltage (6 V, 7.5 V) to operate? What are the considerations needed to be taken into account for this?

Answer: See Example 1 of the previous question.

Question 12: What is the purpose of the GPIO pin in the CYPD3177 device?

Answer: The GPIO pin in the CYPD3177 device can be used as a static control input or as a status output. The GPIO can be configured using HPI commands. See the EZ-PDTM BCR HPI specification for details.

Question 13: Will the EZ-PDTM BCR devices interoperate with a legacy 5-V USB Type-A port?

Answer: Yes, the CYPD3177 device will operate with a legacy 5-V USB Type-A port. You will need to use a USB-C to A cable for this.
However, the CYPD3177 device cannot negotiate other Type-A charging protocols like BC1.2, QC 2.0, Apple charging and Samsung AFC. To support these protocols, please consider switching to CYPD3176 or CYPD3178 devices for your design.

Question 14: What are the differences between the devices in the EZ-PDTM BCR portfolio (CYPD3177, CYPD3176, and CYPD3178)?

Answer: The following table shows the comparison of CYPD3177, CYPD3176, and CYPD3178 devices:

Features​

EZ-PD™ BCR family​

Part number

CYPD3176​

CYPD3177​

CYPD3178​

Integrated Arm® Cortex®-M0 MCU @ 48 MHz

Yes

Yes

Yes

USBPD 3.0

Yes

Yes

No

USBPD role

UFP (power sink)

UFP (power sink)

No

Programmable power supply (PPS)

Yes

No

No

USB Type-C charging (5V@ 0.5A, 0.9A, 1.5A, 3A)

Yes

Yes

Yes

Legacy charging support (BC1.2, AFC, Apple 2.4A, QC 2.0)

Yes

No

Yes

USB data compatible

Yes

Yes

Yes

VBUS gate driver

PFET

PFET

PFET

Supply voltage

3.0V – 24.5V

3.0V – 24.5V

3.0V – 24.5V

VBUS to CC short protection

Yes

Yes

Yes

OVP/UVP

Yes​

Yes​

Yes​

OCP/OTP

Yes

No

No

ESD protection on CC, D+/D-, ±8 kV (contact), ±15 kV (air)

Yes

Yes

Yes

I2C Interface​

1

1

1

EZ-PDTM BCR HPI utility

Yes

Yes

Yes

EZ-PDTM configuration utility

Yes

No

No

Evaluation kit

EZ-PD™ BCR-Plus kit

CY4534

EZ-PD™ BCR kit

CY4533

EZ-PD™ BCR-Lite kit

CY4535

Question 15: What is the purpose of the SAFE_PWR FET in EZ-PDTM BCR applications? Is it mandatory to have it in the design?

Answer: The SAFE_PWR circuit is provided as an alternate power source with lower capabilities (5 V, 900 mA) that is available to the system in the event the desired VBUS output is not available from the power source connected to the BCR sink. It is an optional circuit that may be useful to alert the user to power up a subsystem within the main application to let the user know that the capabilities of the connected power supply cannot meet the power requirements of the application.

Question 16: For CYPD3176 and CYPD3178 based applications that need to interoperate with legacy chargers like QC2.0 and AFC, what are the design considerations for setting ISNK_COARSE and ISNK_FINE values?

Answer: The CYPD3176 and CYPD3178 devices support sink legacy charging protocols when the CHARGING_MODE pin is kept floating. The EZ-PDTM BCR-Plus device supports BC 1.2, QC 2.0 sink (Class B), AFC and Apple charging protocols.
When a non-PD charger is connected, the EZ-PDTM BCR-Plus device can negotiate any of the legacy charging protocols supported by the sink device. The order of priority of negotiation is as follows:
Negotiation sequence: (PD → BC1.2 → AFC → QC2.0 (class B) → Apple → Type-C only)

USB-PD is of higher priority over any of the legacy charging protocols. PD and BC 1.2 detection start simultaneously, but if the power adapter supports PD, PD takes preference over BC 1.2.

When negotiating legacy protocols, the BCR-PLUS device will negotiate voltage and current based on the VBUS_MIN/MAX and ISNK_COARSE/ISNK_FINE settings. It is recommended that ISNK_COARSE + ISNK_FINE ≥ 0.9 A and ISNK_COARSE + ISNK_FINE ≤ 1.5 A to attain the broadest interoperability with legacy chargers.

The following tables help you select the ISNK_COARSE and ISNK_FINE settings.

Table 1. Resistor divider values for coarse setting on operating current (for VDDD = 3.3 V)

Operating current requested for coarse setting (A)

Resistive ratio relative to VDDD = 3.3 V

Suggested pull-up resistor value (kW)

Suggested pull-down resistor value (kW)

Voltage range on pin (mV)

0

0/6

Open

0

0-248

1

1/6

5.1

1

249-786

2

2/6

5.1

2.4

787-1347

3

3/6

5.1

5.1

1348-1920

4

4/6

5.1

10

1921-2778

5

≥5/6

0

Open

≥2779


Table 2. Resistor divider values for fine setting on operating current (for VDDD = 3.3 V)

Operating current requested for fine setting (A)

Resistive ratio relative to VDDD = 3.3 V

Suggested pull-up resistor value (kW)

Suggested pull-down resistor value (kW)

Voltage range on pin (mV)

+0

0/6

Open

0

0-248

+250

1/6

5.1

1

249-786

+500

2/6

5.1

2.4

787-1347

+750

3/6

5.1

5.1

1348-1920

+900

≥4/6

0

Open

≥1921


The theory of selecting ISNK_COARSE + ISNK_FINE ≤ 1.5 A is to widely support QC2 chargers. As per QC2 specification, the minimum current that is needed to support 5 V is 1.5 A.

Question 17: What is the purpose of sink OCP (over current protection) in the CYPD3176 device? How do I enable sink OCP in the CYPD3176 device?

Answer: For most designs, sink OCP may not be required because most of the USB-C power adapters have source over-current protection. For customers who still need additional redundancy and additional protection, sink OCP can be optionally enabled in the CYPD3176 device by making a non-volatile update to the configuration table.
The CYPD3176 device has a low-side current sense amplifier that can be used to sense the return current flowing through the ground path of the system. A 5-mΩ current sense resistor must be added to the path between the CSP pin and the Type-C connector ground.

Using the EZ-PD™ configuration utility, the configuration table can be updated to support sink OCP as Figure 2 shows.

Chelladurai_0-1633071628987.png

 Figure 2. Enabling sink OCP in EZ-PD™ configuration utility

Once the OCP enable field is set to ‘Yes’, additional options are displayed as shown in Figure 3.

Chelladurai_1-1633071715744.png

 Figure 3. Additional options after enabling OCP in EZ-PD™ configuration utility

Question 18: How do I enable sink programmable power supply (PPS) in CYPD3176?

Answer: The EZ-PDTM BCR-Plus device can be used to support sink PPS where a host processor can request appropriate PPS voltages and currents over HPI. This is done by sending the HPI command to initiate the sink PPS request (request message with RDO data). Once the HPI request is successful, the EZ-PDTM BCR-Plus device will send the PPS request messages every nine seconds periodically.

Send the following HPI command from the system controller for the required sink PPS request.

Name
Address
Size

SINK_RDO_REQUEST
0x1054
4 bytes

Field name

R/W

Field offset

Description

Request data object

WO

Byte 0..3

32-bit request data object

Active RDO writing to this register will result in request of PD contract re-negotiation, in little endian order. If PD contract is established using PPS APDO, BCR-PLUS will periodically request this PPS PRDO.

 

Use the following sequence to make a PPS request from the system controller:

  1. The system controller reads port partner’s source PDOs list.
  2. The system controller generates the preferred PPS RDO message according to the port partner’s source PDOs list.
  3. The system controller sends out the desired PPS RDO message.

For example, consider the following scenario: the EZ-PDTM BCR-Plus device connects to a 27-W PPS power adapter (FIXED_PDO_5V@3A, FIXED_PDO_9V@3A, APDO_3.3V-5.9V@3A, APDO_3.3V-11V@3A). The system controller desires to request RDO of 9V @ 1.5A PPS. To implement this, first write the HPI address 0x08 with the register address 0x1054, and PPS RDO request data: 0x4003841E (PPS RDO 9V@1.5A).

Question 19: How do I use CYPD3176 in a wireless charging application?

Answer: CYPD3176 can handle the charging protocol (sink part) of Type-C port including PD3.0 (PPS), BC1.2, Apple, AFC and QC2.0. After the power adapter is attached to the wireless charger, CYPD3176 can get information including charging protocol and voltage, current capability, and power supply supported. The wireless power transmitter chip can read the related information from CYPD3176 over I2C and handle the wireless charging process by sending I2C commands to the CYPD3176 device to request different voltage or voltage and current values. Figure 4 shows the high-level block diagram on how to use CYPD3176 in a wireless charging application.

Figure 4.PNG

 Figure 4. Block diagram for using EZ-PD™ CYPD3176 in wireless charging application

Question 20: Is there a way to measure and report the current consumed by the power sink to a host MCU?

Answer: For applications based on CYPD3176 or CYPD3178, the host MCU can send the HPI command to read the ‘BUS_CURRENT’ register to report the live current consumed.

The details for the HPI register are as follows:

BUS_CURRENT
This read-only status register reports the live current drawn from the VBUS supply for the specified port (in 50-mA units). The current will be measured using the internal ADC and external resistor (5 mΩ).

Name
Address
Size

BUS_CURRENT
0x1058
1-byte

Field name

R/W

Field offset

Description

Current draw from the bus supply

RO

Byte 0

Current

Live Vbus current, in 50-mA units

 

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