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ECC Implementation in Cypress’s 65-nm Asynchronous SRAMs – KBA90940
Question: How is error correcting code (ECC) implemented to mitigate soft errors in Cypress’s 65-nm Asynchronous SRAMs?
Cypress’s 65-nanometer (65-nm) asynchronous SRAM devices use (38, 32) Hamming Code for single-bit error detection and correction. A hardware ECC block performs all ECC-related functions inline, without user intervention and without affecting the access-time performance of the device. The single-bit error detection and correction capability is supplemented by a 16-bit interleaving scheme to minimize the occurrence of multi-bit errors by spreading a physical multi-bit upset to a logical multi-bit upset across multiple words. Together, these features help lower the rate of soft errors below detectable levels. The above architectural and design implementations provide significant improvements in soft-error rate (SER) performance, resulting in failure in time (FIT) rates as low as 0.1 FIT/Mb.
Figure 1 illustrates the internal organization of a 65-nm asynchronous SRAM. In the event of a memory cell corruption due to soft errors, the data read from the corrupted location is corrected and placed on the external I/O bus during a READ operation. The data-word, however, still contains corrupted data because it resides in memory. Over a period of time, multiple singe-event upsets (SEUs) may affect the same word, resulting in an accumulated multi-bit upset (MBU) (two or more SBUs in the same word). To eliminate this problem, the system can implement memory scrubbing, wherein the application periodically rewrites the content in the memory to correct all the soft errors. Cypress’s 65-nm asynchronous SRAM devices include an optional error indication (ERR) signal that indicates the occurrence and correction of single-bit errors only. The system can use this information to recognize the event and write back corrected data.
Figure1. Internal Organization of a 65-nm Asynchronous SRAM
For more information, refer to the following KBAs: