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Differences between WREN (06h) and WRENV (50h) commands for Infineon QSPI Flash families – KBA233510

ArunKumarChoul
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Differences between WREN (06h) and WRENV (50h) commands for Infineon QSPI Flash families – KBA233510

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The Write Enable (WREN 06h) command must be written prior to any command that modifies nonvolatile data. The WREN (06h) command sets the Write Enable Latch (WEL) bit of the Status Register 1 (SR1V[1]) to a “1”. The Write Enable Latch (WEL) bit must be set to a “1” by issuing the WREN (06h) command to enable write, program, and erase commands. CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched. Without CS# being driven to the logic HIGH state after the eighth bit of the instruction byte has been latched, the write enable operation will not be executed. Write Register (WRR) command following WREN (06h) command modifies non-volatile Status Register and Configuration Registers. The volatile Status Register and Configuration Registers are also automatically updated to the same. The WREN (06h) is supported in all Infineon QSPI Flash families.

The Write Enable Volatile (WRENV 50h) command is written prior to Write Register (WRR) command in the case that only modifies volatile Status Register and Configuration Registers. Non-volatile Status Register and Configuration Registers remain unchanged. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical nonvolatile bit write cycles or affecting the endurance of the status or configuration nonvolatile register bits. However, after this operation, the values in volatile and non-volatile Status Register and Configuration Registers may not be the same. Volatile register values decide the flash device behaviors. After power cycle or reset, the volatile registers will be automatically loaded with the values from non-volatile registers.

The WRENV (50h) command will not set the Write Enable Latch (WEL) bit, it is used only to direct the following WRR command to change the volatile status and configuration register bit values. CS# must be driven into the logic HIGH state after the eighth bit of the instruction byte has been latched in on SI/IO0. Without CS# being driven to the logic HIGH state after the eighth bit of the instruction byte has been latched, the write enable operation will not be executed. WRENV (50h) command is only supported in S25FL-L and SEMPER™ Flash with QSPI Interface devices.

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‎Jun 29, 2021 08:11 PM
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