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Difference between wait states, dummy cycles, and read latency for SPI flash - KBA233941
Wait states and dummy cycles are the same. Read latency is superset of wait states (or dummy cycles). Read latency equals the sum of clocks for mode bits and wait states.
To understand the concepts, here are the definitions from JESD216 standard:
Mode bits: Optional control bits that follow the address bits and are driven by the controller if they are specified.
Wait states: Required clock cycles between the address bits or optional mode bits and the start of data when reading from the flash device. Some device data sheets describe these as dummy cycles because no information is transferred between the controller and memory during these cycles. Neither controller nor memory are required to drive the data lines during these cycles.
Read latency: On flash read instructions, the total number of clocks between the end of address and the start of data. The sum of clocks for mode bits and clocks for wait states equals the read latency. Read latency equals dummy cycles (wait states) when mode bits are not specified by controller; see Figure 1. Read latency equals the sum of clocks for mode bits and dummy cycles (wait states) when mode bits are specified by controller; see Figure 2.