Question: 1.How do I create a bidirectional signal in Warp? 2.How do I correctly simulate a bidirectional signal?
Answer: The following VHDL code provides an example on how to create and use a bi-directional signal in Warp.
library IEEE;
use ieee.std_logic_1164.all;
ENTITY tristate IS
PORT (clk : in std_logic; -- clk input
a : in std_logic; -- input to drive b
out_enable : in std_logic; -- input to set state of b (input or output)
b : inout std_logic; -- bidirectional
c : out std_logic); -- c always receives b
END tristate;
ARCHITECTURE behav OF tristate IS
signal tempx : std_logic;
BEGIN
-- First, note that 'Z' can NOT be assigned to an output inside of a clocked process.
-- when targeting Cypress PLD's that do not have registered OE's (370, 370i, 37k)
-- So, we assign the 'Z' to the output asynchronously
b <= tempx when out_enable = '1' else 'Z';
-- assign b to c
c <= b;
outputs: process (clk)
begin
if (clk'event and clk ='1') then
tempx <= a;
end if;
end process;
END behav;
--Placing the oe control inside of the process makes the output enable
--dependant on a clock signal. The error generated by Warp is:
--Error 461 "Output-enable not supported beneath a WAIT"
This code shows that the output of the signal is set to high Z when not in use.
For simulation, the only thing to consider when simulating a bi-directional signal is that the strength of the stimulator for that particular signal must be set to drive and NOT override. Setting the stimulator to override will cause the waveform to simulate improperly.
Please be noted our entire Cypress CPLD and Warp product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld
