Constraints on PSoC 6 MCU Blocking and Partially Blocking Flash Operations – KBA230568

ChaitanyaV_61 · ‎Aug 12, 2020

Author: ShipingW_81 Version: **

Translation - Japanese:PSoC 6 MCUのブロッキングおよびフラッシュオペレーションの部分的なブロッキングに関する制約 – KBA230568 - Community Translated

For PSoC 6 MCU, write operations on user flash are performed on a per-sector basis and may be done as Blocking or Partially Blocking.

Blocking

In this case, the entire flash block is not available for the duration of the write. Therefore, no flash accesses (from any Bus Master) can occur during that time. CPU execution can be performed from SRAM. All pre-fetching must be disabled. Application code execution from flash is blocked for the flash write duration for both cores.

Constraints on Blocking Flash operations

During write to flash, the device should not be reset (including XRES pin, software reset, and watchdog), or unexpected changes may be made to portions of the flash.
The low-voltage detect circuits should be configured to generate an interrupt instead of a reset.
Flash write operation is allowed only in one of the following CM4 states:

a. CM4 is active and initialized:
Call Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR). Note: If required, you may put the CM4 core in Deep Sleep any time after calling Cy_SysEnableCM4().

b. CM4 is OFF:
Call Cy_SysDisableCM4(). Note: In this state, Debug mode is not supported.
Flash write cannot be performed in ULP (core voltage 0.9 V) mode.
Interrupts must be enabled on both active cores. Do not enter a critical section during flash operation.
System pipe interrupts (IPC interrupts 3 and 4) must have the highest priority, or at least pipe interrupts must not be interrupted or in a pending state for more than 700 µs.
During a flash write operation, flash read operations must not be performed by bus masters other than CM0+ and CM4 (DMA and Crypto).
If you do not use the default startup, perform the following steps before any flash write/erase operations:

/* 1. Allocate and initialize IPC semaphores for the system operations */

static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];

(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);

/* 2. Create an array of endpoint structures and configure an IPC pipe infrastructure */

static cy_stc_ipc_pipe_ep_t ipcPipeEpArray[CY_IPC_MAX_ENDPOINTS];

Cy_IPC_Pipe_Config(ipcPipeEpArray);

/* 3. Create an array of client callbacks and initialize a system pipe by a configuration structure */

static cy_ipc_pipe_callback_ptr_t sysIpcPipeCbArray[CY_SYS_CYPIPE_CLIENT_CNT];

static const cy_stc_ipc_pipe_config_t systemIpcPipeConfig =

{

/* .ep0ConfigData */

{

/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,

/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,

/* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,

/* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,

/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0

},

/* .ep1ConfigData */

{

/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,

/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,

/* .ipcNotifierMuxNumber */ 0u,

/* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,

/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1

},

/* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,

/* .endpointsCallbacksArray */ sysIpcPipeCbArray,

/* .systemPipeIsrHandler */ &SysIpcPipeIsr

};

Cy_IPC_Pipe_Init(&systemIpcPipeConfig);

/* 4. And finally initialize the flash */

Cy_Flash_Init();

/* Ensure to run these steps on all the MCU cores */

Partially Blocking

This method has a much shorter time window during flash accesses are not allowed. Application code execution from flash is blocked for only part of flash write duration for both cores. The blocking duration depends on the API sequence used.

Constraints on Partially Blocking Flash operations

During write to flash, the device should not be reset (including the XRES pin, software reset, and watchdog) or unexpected changes may be made to portions of the flash.
The low-voltage detect circuits should be configured to generate an interrupt instead of a reset.
During write to flash, application code must not change the clock settings. Use Cy_Flash_IsOperationComplete() to ensure that the flash write operation is finished.
During write to flash, the application code must not start the clock measurements (should not call Cy_SysClk_StartClkMeasurementCounters()).
The flash write operation is allowed only in one of the following CM4 states:

a. CCM4 is active and initialized:
      Call Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR). Note: If required, you may put the CM4 core in Deep Sleep any time after calling Cy_SysEnableCM4().

b. CM4 is OFF:
      Call Cy_SysDisableCM4(). Note: In this state, Debug mode is not supported.
Use the following rules for split by sectors. (In this context, read means read of any bus master: CM0+, CM4, DMA, Crypto, etc.)

a. Do not write to and read/execute from the same flash sector at the same time. This is true for all sectors.
b. Writing rules in user flash:
I. Any bus master can read/execute from UFLASH S0 and/or S1 during flash write to UFLASH S2 or S3.
II. Any bus master can read/execute from UFLASH S2 and/or S3 during flash write to UFLASH S0 or S1.
Suggestion: In case of bootloading, place the code for CM4 in either S0 or S1. The CM0+ code resides in S0. Write the data to S2 and S3 sections.
Flash write cannot be performed in ULP mode (core voltage 0.9 V).
Interrupts must be enabled on both active cores. Do not enter a critical section during flash operation.
System pipe interrupts (IPC interrupts 3 and 4) must have the highest priority, or at least pipe interrupts must not be interrupted or in a pending state for more than 700 µs.
During a flash write operation, flash read operations must not be performed by bus masters other than CM0+ and CM4 (DMA and Crypto).
If you do not use the default startup, perform the following steps before any flash write/erase operations: