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Configuring a CY8C201xx Device for Use Either with External Pull-ups or With a Master Operating at Different VDD – KBA80735

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Configuring a CY8C201xx Device for Use Either with External Pull-ups or With a Master Operating at Different VDD – KBA80735

Version: *A

Translation - Japanese: 外部プルアップまたは異なるVDDで動作するマスターのいずれかで使用するためのCY8C201xxデバイスの構成 - KBA80735 - Community Translated (JA)

Question: What action must be taken to use a CY8C201xx device either with external pull-ups or with a master operating at different VDD?

Answer:

The CY8C201xx devices support internal pull-up resistors on I2C lines. Table 1 shows the factory default settings for internal pull-up resistors.
 

Table 1: Factory Default Values for Internal Pull-Up Setting
 

                                                           

  
     Device
 
  
     Internal Pull-Up (factory default)
 
    CY8C20111/21  
     Disabled
 
    CY8C201A0  
     Enabled
 
    CY8C20110/80/60/40/42  
     Enabled
 

 
  The setting for the internal pull-up resistors must match the requirements of the overall design. When the setting is incorrect, the following problems can occur:
  

     
  •     Pull-ups should be sized correctly to meet rise time and IOL requirements in an I2C design. Use of internal pull-ups enabled in combination with external pull-ups in a CapSense® device reduces the effective resistance. Proper bus operation is not guaranteed.
  •  
  •     Consider the scenario in which the CapSense device operates at 3.3 V with internal pull-ups enabled while the master operates at 1.8 V and external pull-ups pull the bus to 1.8 V. Bus voltage (VIH) seen by the master is between 1.8 V and 3.3 V due to the voltage divider formed by internal and external pull-ups. This condition can damage the master device.
        
  In the above scenarios, it is recommended to DISABLE the internal pull-up resistor. This has to be done during the device configuration, before soldering it in the end system. To enable or disable the internal pull-up resistors, configure the I2CDM bit (MSB) in the I2C_ADDR_DM (7Ch) register. For more information, see CY8C201xx : Register Reference Guide.
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‎Jul 03, 2012 02:06 AM
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