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Clock Stretching: I2C speed and worst case duration

Clock Stretching: I2C speed and worst case duration

DineshbabuM_66
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How does the I2C clock speed affect the duration of clock stretching introduced by the I2C slave?

 

Clock stretching is a phenomenon where the PSoC I2C slave pulls the SCL line low after the 8th clock of every I2C data/address transfer (before the ACK/NAK stage). The clock is pulled low when the CPU is processing the I2C interrupt to evaluate either the address or process a data received from Master or to prepare the next data when Master is reading from the slave. 

The time the clock is pull low depends on the time the CPU takes to process the interrupt and hence is dependent on the CPU speed and not the I2C clock speed.

 

What is the worst case duration of clock stretching?

 

PSoC when configured to act as an I2C slave pulls the SCL line low soon after the reception of an incoming I2C data byte. An interrupt is accompanied with this event and it is inside the ISR of this interrupt that CPU initiates the release of the clock line by writing appropriate ACK/NAK status to I2C control register.

Worst case time for which the clock stretching occurs can be computed from the equation below. Assumptions:

No of enabled interrupts in the project = N (including the I2C ISR)

Clock Stretching Time = (25Cycles * N) * CPU_CLK + (Sum of execution time of N ISR’s)

Note: Execution time of one ISR can be computed by multiplying CPU clock time with number of CPU clock cycles associated with that ISR

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