JP Translation:S29GL128Pxxのチップイレーズが2つのCMで50秒から65秒に異なる。何が問題なのでしょうか？- KBA203363
Version: **
Question:
Chip Erase differs from 50s to 65s for the S29GL128Pxx at two separate CM locations. What might be the issue?
Answer:
According to the datasheet for the S29GLxxxP, a Chip Erase time of 65secs is typical. However, one difference in the Chip Erase timing may be due to the actual data pattern programmed into the Flash. If there are more ZERO's than ONE's, then the Chip Erase time may be less due to less pre-programming time required. However, if there are more ONE's than ZERO's, then the Chip Erase time may be longer due to more pre-programming required, as any bits that are ONE's (erased) will be pre-programming to ZERO's (programmed); and then erased back to ONE's. Verify and confirm that the actual data patterns programmed into the Flash are identical.
