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Changing the priority of PSoC™ 6 AHB interface masters - KBA233889
The PSoC™ 6 MCU has several Arm®-specified advanced high-performance bus (AHB) interface masters such as Arm® CM4 CPU core, Arm® CM0 CPU core, Datawire0, Datawire1, Crypto, and debug access port (DAP).
Since different bus masters may try to access the bus simultaneously, this makes any access to data movement over the bus subject to arbitration with other masters. Actions such as fetching the descriptor or data can be stalled by arbitration. It is possible to configure the bus arbitration priority setting that these masters have over the AHB.
For example, if you are using both Data Wire 0 and Data Wire 1 in your project, how do you increase the priority of Data Wire 0 over Data Wire 1 or vice versa?
The arbitration of the bus is based on the arbitration scheme configured by the PRIO bits of the PROT_SMPU_MSx_CTL register. Each of the bus masters has a PROT_SMPU_MSx_CTL register corresponding to it. You can increase the priority of the bus by writing '0' (highest priority) to the PRIO bits (bits 8 and 9) of the PROT_SMPU_MSx_CTL register. You can refer to the respective Register TRM of the PSoC™ 6 device for more details.
For information on which PROT_SMPU_MSx_CTL register to write to, refer to the psoc6_02_config.h file (in the case of PSoC™ 62) that is present in the .....project_workspace\mtb_shared\mtb-pdl-cat1\release-v2.2.0\devices\COMPONENT_CAT1A\include directory, as shown in the following image:
The en_prot_master_t enum contains the different bus masters and their corresponding PROT_SMPU_MSx_CTL register.
In the above example, to increase or decrease the bus priority for Data wire 0 you need to write to thePROT_SMPU_MS2_CTL register. Similarly, for the DMA controller, you need to write to the PROT_SMPU_MS4_CTL register.
Note: Masters with the same priority setting form a "priority group". Within a "priority group", round-robin arbitration is performed.