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Change ECC configuration to dual error detection (DED) mode in S26KL/KS-S HYPERFLASH™ - KBA233612

Chelladurai
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Change ECC configuration to dual error detection (DED) mode in S26KL/KS-S HYPERFLASH™ - KBA233612

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You can enable the DED mode by programming ‘0’ to the ASP configuration register bit 9 (ASPR[9]).

Consider the following precautions when enabling the DED mode:

  1. ASPR holds non-volatile and one-time programmable (OTP) bits. After enabling the DED mode by programming ‘0’ to ASPR[9], you cannot revert the bit back to ‘1’.
  2. In the DED mode, multiple program operations to the same 16-byte half-page (without an erase) are not allowed. Attempting to program more than once in the same 16-byte half-page will result in program failure.
  3. Programming any data to flash before enabling the DED mode generates the ECC for that data based on the single-bit error correction (SEC) scheme. Reading SEC-based ECC by the DED scheme will result in an undefined behavior. Therefore, non-blank sectors must be erased before changing the ECC configuration to DED mode.
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Last update:
‎Aug 25, 2021 01:53 AM
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