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Block Protection Configuration on FL-S and FS-S NOR Flash – KBA224451

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Block Protection Configuration on FL-S and FS-S NOR Flash – KBA224451

Author: Vincenth_06          Version: **

Translation - Japanese: FL-SおよびFS-SNORフラッシュのブロック保護設定– KBA224451 - Community Translated (JA)

Question:

How can I implement and configure basic block protection on FL/S-S devices?

Answer:

Cypress provides the basic block protection function to write-protect all or a part of memory array on FL-S and FS-S devices. The selectable protected area can be configured, and the position can be either on top (high address) or bottom (low address) of the flash.

Table 1. Upper Array Start of Protection (TBPROT=0)

Status Register Content

Protected Fraction of Memory Array

Protected Memory (KB)

BP2

BP1

BP0

FL/S128S
128 Mb

FL/S256S
256 Mb

FL/S512S
512 Mb

0

0

0

None

0

0

0

0

0

1

Upper 64th

256

512

1024

0

1

0

Upper 32nd

512

1024

2048

0

1

1

Upper 16th

1024

2048

4096

1

0

0

Upper 8th

2048

4096

8192

1

0

1

Upper 4th

4096

8192

16384

1

1

0

Upper Half

8192

16384

32768

1

1

1

All Sectors

16384

32768

65536

Table 2. Lower Array Start of Protection (TBPROT=1)

Status Register Content

Protected Fraction of Memory Array

Protected Memory (KB)

BP2

BP1

BP0

FL/S128S
128 Mb

FL/S256S
256 Mb

FL/S512S
512 Mb

0

0

0

None

0

0

0

0

0

1

Lower 64th

256

512

1024

0

1

0

Lower 32nd

512

1024

2048

0

1

1

Lower 16th

1024

2048

4096

1

0

0

Lower 8th

2048

4096

8192

1

0

1

Lower 4th

4096

8192

16384

1

1

0

Lower Half

8192

16384

32768

1

1

1

All Sectors

16384

32768

65536

The protection can be configured by setting Status and Configuration Registers. However, there are some differences between FL-S and FS-S devices.

For FL-S devices, the SR1 and CR1 should be configured according to the device datasheet.

Table 3. FL-S Status Register 1 (SR=1)

Bits

Field Name

Function

Type

Default State

Description

7

SRWD

Status Register Write Disable

Nonvolatile

0

1 = Locks the state of SRWD, BP, and configuration register bits when WP# is LOW by ignoring the WRR command.
0 = No protection, even when WP# is LOW

6

P_ERR

Programming Error Occurred

Volatile, Read only

0

1 = Error occurred
0 = No Error

5

E_ERR

Erase Error Occurred

Volatile, Read only

0

1= Error occurred
0 = No Error

4

BP2

Block Protection

Volatile if CR1[3]=1, Nonvolatile if CR1[3]=0

1 if CR1[3]=1, 0 when shipped from Cypress

Protects the selected range of sectors (Block) from Program or Erase.

3

BP1

2

BP0

1

WEL

Write Enable Latch

Volatile

0

1 = Device accepts Write Registers (WRR), program or erase commands.
0 = Device ignores Write Registers (WRR), program or erase commands.
This bit is not affected by WRR; only WREN and WRDI commands affect this bit.

0

WIP

Write in Progress

Volatile, Read only

0

1= Device Busy, a Write Registers (WRR), program, erase or other operation is in progress.
0 = Ready Device is in standby mode and can accept commands

Table 4. FL-S Configuration Register 1 (CR=1)

Bits

Field Name

Function

Type

Default State

Description

7

LC1

Latency Code

Nonvolatile

0

Selects the number of initial read latency cycles.
See Latency Code Tables.

6

LC0

0

5

TBPROT

Configures Start of Block Protection

OTP

0

1 = BP starts at bottom (Low address).
0 = BP starts at top (High address).

4

RFU

RFU

OTP

0

Reserved for Future Use.

3

BPNV

Configures BP2-0 in Status Register

OTP

0

1 = Volatile
0 = Nonvolatile

2

TBPARM

Configures Parameter Sectors location

OTP

0

1 = 4-KB physical sectors at top, (high address).
0 = 4-KB physical sectors at bottom (Low address).
RFU in uniform sector devices

1

QUAD

Puts the device into Quad I/O operation

Nonvolatile

0

1 = Quad
0 = Dual or Serial

0

FREEZE

Lock current state of BP2-0 bits in Status Register, TBPROT and TBPARM in Configuration Register, and OTP regions

Volatile

0

1 = Block Protection and OTP locked.
0 = Block Protection and OTP unlocked.

  • SR1[4:2] (BP2-0) defines the protection scope.
  • CR1[5] (TBPROT) defines the block protection position on top or bottom.
  • CR1[3] (BPNV) defines the property of BP2-0 in SR1[4:2], when BPNV=0, BP2-0 is nonvolatile and the configuration can survive after POR; when BPNV=1, the BP2-0 is volatile and value is always reset to 111b after power-on reset (POR).
  • CR1[0] (FREEZE) can lock the BP2-0, TBPROT, and BPNV bits from unexpected modification until the next POR; any modification of these bits will report an error and will fail when FREEZE=1. the FREEZE bit is volatile and is reset to 0 after POR.

Note that the BPNV and TBPROT bits are OTP bits which can only set from ‘0’ to ‘1’ once and cannot be changed back anymore. Make sure you pay attention when configuring these bits. The WREN command must be applied to enable the further WRR command before configuring the SR and CR.

It is a good practice to set the FREEZE bit to ‘1’ after you modify block protection configurations. Once the FREEZE bit is written to ‘1’, it can only be cleared to ‘0’ by POR or a hardware reset. Software reset will not affect the state of the FREEZE bit. This can prevent further unexpected changes and hacking.

For FS-S devices, SR1(N)V and CR1(N)V should be configured according to the device datasheet.

Table 5. FS-S Status Register 1 Volatile (SR1V)

Bits

Field Name

Function

Type

Default State

Description

7

SRWD

Status Register Write Disable

Volatile Read Only

SR1NV

Volatile copy of SR1NV[7].

6

P_ERR

Programming Error Occurred

Volatile Read Only

1 = Error occurred.
0 = No Error.

5

E_ERR

Erase Error Occurred

Volatile

1 = Error occurred.
0 = No Error.

4

BP2

Block Protection Volatile

Volatile

Protects the selected range of sectors (Block) from Program or Erase when BP bits are configured as volatile (CR1NV[3]=1). It is the Volatile copy of SR1NV[4:2] when BP bits are configured as non-volatile. User writable when BP bits are configured as volatile.

3

BP1

2

BP0

1

WEL

Write Enable Latch

Volatile

1 = Device accepts Write Registers (WRR and WRAR), Program, or Erase commands.
0 = Device ignores Write Registers (WRR and WRAR), Program, or Erase commands.
This bit is not affected by WRR or WRAR, only WREN and WRDI commands affect this bit.

0

WIP

Write-In-Progress

Volatile Read Only

1= Device Busy, an embedded operation is in progress such as Program or Erase.
0 = Ready Device is in Standby mode and can accept commands.
This bit is not affected by WRR or WRAR, it only provides WIP status.

Table 6. FS-S Status Register 1 Non-Volatile (SR1NV)

Bits

Field Name

Function

Type

Default State

Description

7

SRWD_NV

Status Register Write Disable Default

Nonvolatile

0

1 = Locks state of SRWD, BP, and Configuration Register 1 bits when WP# is low by not executing WRR or WRAR commands that would affect SR1NV, SR1V, CR1NV, or CR1V.
0 = No protection, even when WP# is low.

6

P_ERR_D

Programming Error Default

Nonvolatile
Read Only

0

Provides the default state for the Programming Error Status. Not user programmable.

5

E_ERR_D

Erase Error Default

Nonvolatile
Read Only

0

Provides the default state for the Erase Error Status. Not user-programmable.

4

BP_NV2

Block Protection Non-Volatile

Nonvolatile

000b

Protects the selected range of sectors (Block) from Program or Erase when BP bits are configured as nonvolatile (CR1NV[3]=0). Programmed to 111b when BP bits are configured to volatile (CR1NV[3]=1),  after which these bits are no longer user-programmable.

3

BP_NV1

2

BP_NV0

1

WEL_D

WEL Default

Nonvolatile
Read Only

0

Provides the default state for WEL Status. Not user-programmable.

0

WIP_D

WIP Default

Nonvolatile
Read Only

0

Provides the default state for WIP Status. Not user-programmable.

Table 7. FS-S Configuration Register 1 Volatile (CR1V)

Bits

Field Name

Function

Type

Default State

Description

7

RFU

Reserved for Future Use

Volatile

CR1NV

  1. Reserved.

6

RFU

5

TBPROT

Volatile copy of TBPROT_O

Volatile
Read Only

Not user-writable.
See CR1NV[5] TBPROT_O.

4

RFU

Reserved for Future Use

RFU

  1. Reserved.

3

BPNV

Volatile copy of BPNV_O

Volatile
Read Only

Not user-writable.
See CR1NV[3] BPNV_O.

2

TBPARM

Volatile copy of TBPARM_O

Volatile
Read Only

Not user writable.
See CR1NV[2] TBPARM_O.

1

QUAD

Quad I/O Mode

Volatile

1 = Quad.
0 = Dual or Serial.

0

FREEZE

Lock-Down Block Protection until next power cycle

Volatile

Locks the current state of Block Protection control bits and OTP regions.
1 = Block Protection and OTP locked.
0 = Block Protection and OTP unlocked.

Table 8. FS-S Configuration Register 1 Nonvolatile (CR1NV)

Bits

Field Name

Function

Type

Default State

Description

7

RFU

Reserved for Future Use

Nonvolatile

0

  1. Reserved.

6

RFU

0

5

TBPROT_O

Configures Start of Block Protection

OTP

0

1 = BP starts at bottom (Low address).
0 = BP starts at top (High address).

4

RFURFU

Reserved for Future Use

RFU

0

  1. Reserved.

3

BPNV_O

Configures BP2-0 in Status Register

OTP

0

1 = Volatile.
0 = Nonvolatile.

2

TBPARM_O

Configures Parameter Sectors location

OTP

0

1 = 4-KB physical sectors at top, (high address).
0 = 4-KB physical sectors at bottom (Low address).
RFU in uniform sector configuration.

1

QUAD_NV

Quad Nonvolatile

Nonvolatile

0

Provides the default state for the QUAD bit.

0

FREEZE_D

FREEZE Default

Nonvolatile
Read Only

0

Provides the default state for the Freeze bit. Not user-programmable.

  • SR1V[4:2] (BP2-0) defines the protection scope for the volatile version.
  • SR1NV[4:2] (BP_NV2-0) defines the protection scope for the nonvolatile version.
  • CR1NV[5] (TBPROT_O) defines the block protection position on top or bottom.
  • CR1NV[3] (BPNV_O) defines the copy of BP configurations that take effect on the device; when BPNV_O=0, nonvolatile BP_NV2-0 will take effect; when BPNV_O=1, volatile BP2-0 will take effect.
  • CR1V[0] (FREEZE) can lock BP2-0/BP_NV2-0, TBPROT_O, and BPNV_O bits from unexpected modification until the next POR; any modification of these bits will report error and will fail when FREEZE=1. the FREEZE bit is volatile and reset to ‘0’ after POR.

Note that BPNV_O and TBPROT_O bits are OTP bits that can be set from ‘0’ to ‘1; only once and cannot be changed back anymore. Make sure to pay attention when configuring these bits. The WREN command must be applied to enable further WRR and WRAR commands before configuring the SR and CR.

It is a good practice to set the FREEZE bit to ‘1’ after you modify block protection configurations. Once the FREEZE bit is written to ‘1’, it can be cleared to ‘0’ only by POR or a hardware reset. Software reset will not affect the state of the FREEZE bit. This can prevent further unexpected changes and hacking.

Note for FS01GS devices:

This device consists of dual-die stack; with only one CS# pin, some commands, such as WRR, RDSR1, and RDCR, without specific address cycles are not supported. WRAR and RDAR commands with the corresponding registers’ 4-byte address on each FS512S die are used for block protection configuration. Block protection must be configured in each FS512S as required to protect the sectors in each die. Note that because TBPROT_O bits in each FS512S must be configured the same, the BP protection range is oriented from top or bottom in both FS512S dies.

Block protection is the basic protection function on Cypress QSPI NOR flash devices. To achieve some complex and flexible protection on individual sectors, the Advanced Sector Protection (ASP) function is required. For more information about the ASP function, see AN98551 - Advanced Sector Protection (ASP) in Cypress Quad SPI, Octal SPI, and HyperFlash Device Fam....

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