Answer:
This KB pertains to the /BUSY and /INT pins implementation on SPCM Asynchronous Dual Port SRAMs CY7C131E/131AE/136E/136AE (RAM42) which are being offered as an alternative for the CY7C131/131A/136/136A (RAM28) parts.
The RAM28 parts have an open drain configuration for the /BUSY signal which can be tied together to obtain a wired OR capability. Please refer to Figure 1, which depicts an architecture in which the /BUSY signals of two dual port SRAMs have been shorted together to generate a composite /BUSY signal.
Figure 1. RAM28 device /BUSY pin configuration – open drain
The new RAM42 devices have push-pull /BUSY and /INT signals and the DPSRAM actively drives the line to logic levels ‘1’ or ‘0’. If two /BUSY signals having push pull configuration are shorted, the composite /BUSY signal tends to settle at an intermediate level. This may cause spurious interrupts or it may never trigger an interrupt to the controller.
The logic conditions to be considered are:
DPSRAM_1 /BUSY flag | DPSRAM_2 /BUSY flag | Expected Composite /BUSY flag | Actual Composite /BUSY flag |
0 (active) | 0 (active) | 0 (active) | 0 (active) |
0 (active) | 1 (inactive) | 0 (active) | Intermediate voltage level |
1 (inactive) | 0 (active) | 0 (active) | Intermediate voltage level |
1 (inactive) | 1 (inactive) | 1 (inactive) | 1 (inactive) |
Application workaround:
External glue logic (as shown in Figure 2) is required to ensure that /BUSY signals from multiple devices are properly interpreted by the CPU/FPGA.
Figure 2. RAM42 device /BUSY pin configuration – push - pull configuration
Any expansion configuration or systems in which multiple /BUSY or /INT signals with a push pull I/O architecture are tied together, must be modified to include the glue logic to avoid misinterpretation of the /BUSY and /INT signals at the receiver.