Analysis of CX3 Clocking Parameters – KBA226758

[Community-Team]

Author: abhinavg_21            Version: **

The CX3 MIPI configuration tool has various types of clocks, which serve different purposes. This KBA explains all the internal clocks of MIPI block and the parameters needed to generate them.

Figure 1: Clocking Diagram of MIPI Block in CX3

1. Ref Clock: The reference clock is provided externally and has a range of 6 MHz to 40 MHz. It is used to generate all the internal clocks required for working of the MIPI block.
   
   
2. Unit Clock: REF CLK / Pre-divider value / 2^{frequency selection} 
   
   
3. PLL Out Clock: To generate this clock, program the PLL block inside the MIPI block. The CX3 config tool generates three parameters in the MIPI config structure (FRS, PRD, and FBD) to program the PLL block.
   
   

   a.    Frequency Range Selection (FRS): It depends on the output range of the PLL clock. This value ranges from 0 (500M – 1G) to 3 (62.5M – 125M).

   b.    Pre-divider value (PRD): It is the pre-divider value (as shown in Figure 1) – 1. ‘1’ is subtracted as the range starts from 0. The PRD range is between 0 and 0x0F.

   c.    Feedback divider (FBD): It is the multiplier of the unit clock (shown in Figure 1) – 1. Minimum and maximum specifications can be calculated using min and max range of the PLL clock. The FBD range is between 0 and 0x1FF.  
   
   

4. CSI RX  LP<->HS Clock: This clock is used for the MIPI D-PHY receiver link establishment. The maximum value for this clock is 125 MHz.
     
   
5. MCLK: It is provided to the external sensor for  testing purposes. Note that this clock should not be used for final production because it has some jitter issues. The CX3 config tool does not provide any parameter to program this clock. If you want to generate  this clock, make the following changes in the generated
   CyU3PMipicsiCfg_t structure.     
   
   

   CyU3PMipicsiCfg_t cfgUvc5Mp15NoMclk =  {

       CY_U3P_CSI_DF_YUV422_8_2,

       2,

       1,

       64,

       CY_U3P_CSI_PLL_FRS_500_1000M,

       CY_U3P_CSI_PLL_CLK_DIV_8,

       CY_U3P_CSI_PLL_CLK_DIV_8,

       0xFFFF,     // ‘MCLK counter’ Change this from zero to a non-zero value. MSB acts as High

       counter & LSB acts as Low counter. Set the Duty Cycle using the MCLK counter.

       CY_U3P_CSI_PLL_CLK_DIV_8, /// Set the MCLK frequency using this divider value.

      
   2592,

       0x01

   };

   MCLK high and MCLK low in Figure 1 are the MSB and LSB of the MCLK counter parameter. This parameter by default is set to zero and hence no clock will be generated on this pin.

   Take any CX3 default example and make the two changes mentioned above in the mipicsicfg structure; it will generate MCLK on the G3 pin of CX3.
   
   

6. Parallel Clock: This is the parallel interface clock that runs the fixed GPIF state      machine. With each edge of this clock, the number of bits (specified by      the output data format of the config structure) will be sent by the MIPI      block from the parallel bus. Note that the config structure data does not      affect the actual output data format; this parameter is used to set the      number of bits sent towards the GPIF side at one edge of the parallel  clock.