cancel
Showing results for 
Search instead for 
Did you mean: 

Knowledge Base Articles

Analog Subsystem of CY8C62x4 Devices - KBA231245

ArunKumarChoul
Employee

Analog Subsystem of CY8C62x4 Devices - KBA231245

Version: *A

Question:
What are the differences in analog subsystem of CY8C62x4 devices as compared to other PSoC 6 devices?

Answer:
CY8C62x4 devices include an advanced analog subsystem designed for low-power analog sensing and simultaneous sampling applications. It has the following new features:

  • Two SAR ADCs capable of simultaneous sampling. It is useful for applications such as Field Oriented Control (FOC) of 3-phase AC motors and RMS power measurements.
  • Both the SAR ADCs are capable of operating in System Deep Sleep mode. This feature enables creating low-power solutions wherein external signals are measured periodically while the rest of the resources in the device are in deep sleep. SAR ADCs in deep sleep mode operate in duty-cycled fashion. It remains OFF while waiting for trigger to start the conversion; upon trigger, the conversion process is started, and once complete, the SAR ADC power is turned OFF again, improving power efficiency.

    To allow deep sleep operation, the following additional functions are included:

    • Deep Sleep Clock domain with Low-Power Oscillator (LPOSC) as one of the clock sources to run the SAR ADCs
    • 16-bit timer to generate periodic triggers to SAR ADCs
    • 64-samples-deep FIFO included to store the results of the SAR ADCs and generate interrupts on certain conditions to wake up the CPU. Each SAR ADC has its own FIFO which can be chained.
  • SAR ADCs can be configured to scan multiple times per trigger
  • CTBm opamp can be configured to duty cycle independently with respect to the SAR ADC. When duty cycled in System Deep Sleep mode along with the SAR ADC, it will be in synchronous with the SAR ADC, thereby reducing the power consumption.
  • CTBm opamp pump clock can be enabled in System Deep Sleep mode to increase the input voltage range of opamps.

The following table provides a summary of available features in PSoC CY8C62x4 and other PSoC 6 MCU devices with respect to the analog blocks:

Features

PSoC CY8C62x4

Other PSoC 6 MCU devices*

Number of SAR ADCs

2

1

Maximum sample rate

2Msps

1Msps/2Msps**

SAR ADC in System Deep Sleep mode

Yes

No

FIFO

Yes

No

Dedicated Timer for SAR ADCs

Yes

No

Low-Power Oscillator (LPOSC)

Yes

No

Configurable number of scans per trigger

Yes

One scan per trigger or continuous scan

Analog Reference in System Deep Sleep mode

Yes

Yes

CTBm Opamp in System Deep Sleep mode

Yes

Yes

CTBm Opamp pump clock active in System Deep Sleep mode

Yes

No

Continuous-Time DAC (CTDAC) output hold in System Deep Sleep mode

Yes

Yes

 

* Some of the device families may not include certain features.
** Maximum sample rate depends on the device family.

See Device Datasheets and Technical Reference Manuals for details.

0 Likes
Version history
Revision #:
1 of 1
Last update:
‎Jun 02, 2021 11:07 PM
Updated by:
 
Contributors