tCMS timing restriction (refresh interval) implementation in Host MCU

[Anonymous]

Dear All,

we have integrated S27KL0641DABHI023 HyperRAM with STM32L4R5ZI  MCU . ( Circuit design is complete & PCB board in fabrication phase )

But while going through datasheet & application note of HyperRAM , I found following note

"The host must also leave the device enough time to perform these operations by keeping the length of the accesses it makes to a safe length .

The tCMS, CS# LOW maximum time, describes the maximum amount of time the host can access the device and still allow the self-refresh logic to operate.

tCMS ~ 4us. "

I am not getting how to fulfill this strange requirement of tCMS as main intention to use hyperram is to read/ write bulk amount of data in external ram .

Also how to calculate time required for each read write operation in program & break operating to respect tCMS timing . it is practically impossible task as most of the time data which need to be read / write is dynamic so cant predict whether operation time will exceed 4us or not .

Also situation becomes worst when Host MCU is operated with low frequency ( 8 , 16 MHz )

request you to please explain how to interface HyperRAM & program for bulk data read write .

Note : refer attached reference manual of Host MCU , section 19 Octo-SPI interface (OCTOSPI)

Regards,

Gaurav