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Dear Support team ,
Thia is with reference to past discussion with Takahiro . tCMS timing restriction (refresh interval) implementation in Host MCU
We have successfully integrated S27KL0641DABHI023 HyperRAM with STM32L4R5ZI MCU and able to read & write data .
but for some frequency setting we are getting garbage data from HyperRAM for first two bytes .
please refer attached document having details of 3 test case ( case no 3 having issue of first two bytes garbage )
Thanks,
Gaurav
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Hi Gaurav,
Sorry my reply is late.
Since the HyperRAM is working in Case 1 (36.67 MHz) the fundamentals like HW connection and the HyperRAM itself should be OK. The issue happens when you change the host controller configuration so this more likely a host controller side issue and this seems not my area...
I would recommend you to contact STM about this. Personally, I feel strange that you are using same clock frequency for both system and OSPI. In general, the system clock should be higher than peripheral clock.
Thanks,
Takahiro