Is it possible to convert the Verilog S27KkL0642.v Model into a netlist?
I have been using the S27KL0642.v model very successfully with the Intel Starter ModelSim Simulator. However, my design has grown to the point that it is very painfully slow. My design is entirely written in VHDL except for the s27KL0642.v Model. I also have a copy of Modelsim PE with a VHDL License which run much faster. I am wondering if I can get a universal netlist version of the S27KL0642 Model that would allow me to use my copy of ModelSim PE with the VHDL License to simulate my design using the netlist version of the S27KL0642 Model instead of the Verilog version??????????????????????Show Less
In studying the Hyper Ram Bus Specifications and the timing of the bus signals specifically the relationship between RWDS and the 8 Data bits, I am not sure how to reliably clock the read data into my Intel/Altera FPGA. I occurs to me that what is needed is a 3 or 4 ns delay line or a 90 degree phase shift to delay the RWDS strobe until the data is stable.
It is evident that this problem can be solved by the availability of Hyper Ram Controllers. Is there any available information on how this is typically accomplished???
I am looking for a Verilog or VHDL Simulation Model for a Hyperram memory device. Does it exist? I am using the IS66WVH16M8ALL-166B1LI device, but any Hyperram Simulation Model will work for my purposes.
The demo showcases the HyperRAM in Industrial or consumer HMI application as an expansion Memory in Display Applications. This demo demonstrates the HyperRAM throughput and density-fit in HMI applications in a low pin count compared to traditional SDR or parallel Async interface PSRAM solutions.
This is home automation where RGB LED (light, intensity), FAN speed, Temperature are remotely controlled/monitored by the HMI unit.
HMI unit uses a TFT display of size 480x272, 16-bit RGB pixel. This corresponds to 2Mbit per frame. Since display is SRAM intensive, internal SRAM is not sufficient in mid range controllers. The external HyperRAM memory is used for display buffer due to low pin count and high throughput.
Demo uses double buffering scheme where one frame is used to update anew display content while the other frame is directly driving the display content. Both frames are stored in HyperRAM. With high throughput of the HyperRAM demo, theoretically it can achieve up to 150fps.
For more details on HyperRAM Memory, click here.
How many mixed of HyperRAM / HyperFlash can exist on the same bus? What are the limitations and critical points?
2x HyperRAM + 1 x HyperFlash
1x HyperRAM + 2 x HyperFlash
I working on some hardware that will use the S70K HyperRAM.
The hardware guide for HyperRAM, where it talks about layout requirements and such, makes a vague reference to using terminations if required. I don't have access to signal integrity tools so I have no way of knowing if the termination resistors will be required or not. My board will be pretty small (less than 1" x 2"), so I will place the RAM as close to the MCU as physically possible.
One of the demo kits for a microcontroller I am considering (STM32H7 variant) places series resistors at the HyperRAM pins only. As the data pins are bidirectional, I'm not sure why the terminations would only be needed in one direction (in this case RAM->MCU but not MCU->RAM).
Does anyone have any advice?Show Less
I am working on iMX8QXP based custom board with Yocto L5.4.24-2.1.0.
On our board, we are trying to communicate S27KS0641 HyperRAM using the FlexSPI interface. I did not find any driver specific to this which I can use.
So I have created my own driver inspired by spi_nor.c. After adjusting the dummy bytes I am able to read the ID register, read-write the Configuration register. But I am not able to correctly(with 100% accuracy) read-write data to/from memory.
Is there anything I am doing wrong?
Is there any driver which uses hyperbus interface and communicates to the memory connected to the flexSPI interface?
My application will use a NXP imxRT1050 FlexSPI summunication with two memory devices:
Cypress Document AN211622, section 4.1 recommends that the connecting transmission lines have 50 ohms characteristic impedance.
The question: Why 50 ohms characteristic impedance? Neither the memory device drivers and receivers nor, insofar as I know, the FlexSPI port drivers and receivers, have 50 homs characteristic impedance.Show Less
HyperRAM has two device technologies.
- 63nm DRAM Process Technology
- 38nm DRAM Process Technology
Are there any functional differences between them?
I understand that the speed is different.
I am wondering if the commands and usage are different.Show Less
I was hoping to do some preliminary development with HyperRAM and a Xilinx FPGA, but am having some trouble finding anything pre-built. I found one option, the S7 mini, but the distributor says that they won't have any more units until February 2021. I wrote Cypress, who linked me up to someone at Avnet (who also deals with Xilinx), and they were unaware of any other boards. So as a last ditch effort to make sure I turned over every rock, I figured I would check here before I give up. Thanks.Show Less