The demo showcases the HyperRAM in Industrial or consumer HMI application as an expansion Memory in Display Applications. This demo demonstrates the HyperRAM throughput and density-fit in HMI applications in a low pin count compared to traditional SDR or parallel Async interface PSRAM solutions.
This is home automation where RGB LED (light, intensity), FAN speed, Temperature are remotely controlled/monitored by the HMI unit.
HMI unit uses a TFT display of size 480x272, 16-bit RGB pixel. This corresponds to 2Mbit per frame. Since display is SRAM intensive, internal SRAM is not sufficient in mid range controllers. The external HyperRAM memory is used for display buffer due to low pin count and high throughput.
Demo uses double buffering scheme where one frame is used to update anew display content while the other frame is directly driving the display content. Both frames are stored in HyperRAM. With high throughput of the HyperRAM demo, theoretically it can achieve up to 150fps.
For more details on HyperRAM Memory, click here.Show Less
How many mixed of HyperRAM / HyperFlash can exist on the same bus? What are the limitations and critical points?
2x HyperRAM + 1 x HyperFlash
1x HyperRAM + 2 x HyperFlash
I working on some hardware that will use the S70K HyperRAM.
The hardware guide for HyperRAM, where it talks about layout requirements and such, makes a vague reference to using terminations if required. I don't have access to signal integrity tools so I have no way of knowing if the termination resistors will be required or not. My board will be pretty small (less than 1" x 2"), so I will place the RAM as close to the MCU as physically possible.
One of the demo kits for a microcontroller I am considering (STM32H7 variant) places series resistors at the HyperRAM pins only. As the data pins are bidirectional, I'm not sure why the terminations would only be needed in one direction (in this case RAM->MCU but not MCU->RAM).
Does anyone have any advice?Show Less
I am working on iMX8QXP based custom board with Yocto L5.4.24-2.1.0.
On our board, we are trying to communicate S27KS0641 HyperRAM using the FlexSPI interface. I did not find any driver specific to this which I can use.
So I have created my own driver inspired by spi_nor.c. After adjusting the dummy bytes I am able to read the ID register, read-write the Configuration register. But I am not able to correctly(with 100% accuracy) read-write data to/from memory.
Is there anything I am doing wrong?
Is there any driver which uses hyperbus interface and communicates to the memory connected to the flexSPI interface?
My application will use a NXP imxRT1050 FlexSPI summunication with two memory devices:
Cypress Document AN211622, section 4.1 recommends that the connecting transmission lines have 50 ohms characteristic impedance.
The question: Why 50 ohms characteristic impedance? Neither the memory device drivers and receivers nor, insofar as I know, the FlexSPI port drivers and receivers, have 50 homs characteristic impedance.Show Less
HyperRAM has two device technologies.
- 63nm DRAM Process Technology
- 38nm DRAM Process Technology
Are there any functional differences between them?
I understand that the speed is different.
I am wondering if the commands and usage are different.Show Less
I was hoping to do some preliminary development with HyperRAM and a Xilinx FPGA, but am having some trouble finding anything pre-built. I found one option, the S7 mini, but the distributor says that they won't have any more units until February 2021. I wrote Cypress, who linked me up to someone at Avnet (who also deals with Xilinx), and they were unaware of any other boards. So as a last ditch effort to make sure I turned over every rock, I figured I would check here before I give up. Thanks.Show Less
Can you guide me, please? I am going to use these 5 memories (include HyperRAm and HyperFlash) by HyperBus interface:
1. 64 Mb HyperRAM Self-Refresh DRAM (S27KL0642/S27KS0642)
2. 128 Mb HyperRAM Self-Refresh DRAM (S70KL1282/S70KS1282)
3. 512 Mb HyperFlashTM (S26KL512S/S26KS512S)
4. 256 Mb HyperFlashTM (S26KL512S/S26KS512S)
5. 128 Mb HyperFlashTM (S26KL512S/S26KS512S)
Are all these 5 memories pin-to-pin compatible, so they can be used with the same ZIF socket?
Thank you and regards,
I'm having trouble to test the Hyperbus Memory Controller IP which downloaded from cypress. I have read the ReadMeFirst pdf file and conducted the neccesary instructions. Yet there occurs some problems about .pl files I believe. The created log file only includes rpc2_ctrl_....... => UNDO. I am not sure whether simulation is successful or not. I want to observe a waveform of test. So if you have an example project (vivado) about test or simulation for Hyperbus Controller IP, could you share it with me?