Hyper RAM

We are considering incorporating the Hyper-RAM S27KS0642GABHV020 (and later the 128-Mbit counterpart) as the DRAM solution in our upcoming product design. The IC will be clocked at 150 MHz. In each transaction, we would like to store/read data in 1024 KB chunks, using Linear Burst Mode (essentially each transaction will read/write a row). Beside the Tcsm limitation, which limits each transaction to 600 cycles when using 150 MHz clock, is there a limit to the number of bytes that can be read or written in a transaction when using Linear Burst Mode? Is our use-case, which requires 527 cycles and respects Tcsm, viable?

Kind regards,
DM_Y

This isn't a HyperRAM question in particular, but this seems like the best place to post this.  I am working on a Xilinx FPGA design that is interfacing with an STM32H microcontroller.  We were hoping to operate in HyperBus mode (which the microcontroller supports), but with the FPGA as the slave.  I know from this thread that Cypress did not supply a slave version of their IP core in 2019, but I was hoping that that might have changed by now: https://community.cypress.com/t5/Hyper-RAM/Using-an-FPGA-as-a-HyperBus-slave/m-p/136850#M84

It appears to me that the only way forward is to design a core by hand, but I was hoping to avoid that if possible.

Is it possible to convert the Verilog S27KkL0642.v Model into a netlist?

I have been using the S27KL0642.v model very successfully with the Intel Starter ModelSim Simulator.  However, my design has grown to the point that it is very painfully slow.  My design is entirely written in VHDL except for the s27KL0642.v Model.  I also have a copy of Modelsim PE with a VHDL License which run much faster.  I am wondering if I can get a universal netlist version of the S27KL0642 Model that would allow me to use my copy of ModelSim PE with the VHDL License to simulate my design using the netlist version of the S27KL0642 Model instead of the Verilog version??????????????????????