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Hyper RAM

New Contributor

Hi,

I'm having trouble to test the Hyperbus Memory Controller IP which downloaded from cypress. I have read the ReadMeFirst pdf file and conducted the neccesary instructions. Yet there occurs some problems about .pl files I believe. The created log file only includes rpc2_ctrl_....... => UNDO.  I am not sure whether simulation is successful or not. I want to observe a waveform of test. So if you have an example project (vivado) about test or simulation for Hyperbus Controller IP, could you share it with me?

Thank you,

Berke.

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