I am testing the S27KS0642GABHI020 on our board with Lattice crosslink-NX FPGA. I have 2 hyperbus controllers to use, one is the cypress hyperbus 2.0 controller and the other is a much simpler one from Lattice. I firstly tried the one from Lattice, I found no matter what I wrote into address 0 I always read back random data, even I didn't write. To avoid the wrong initial latency issue, I looked at the incoming data waveform from Lattice Radiant Reveal logic analyzer, they are always random data (mostly 8'h15). I also probed pins with scope to confirm data is coming from HyperRam. HyperRAM is running at 60MHz, but I also tried as low as 24MHz or higher at 120MHz, all similar results on reading.
What should I check? I also tried manual reset for Hyperram after power up.
1) Can you provide us the schematics of the Hyper ram portion so that we can evaluate it once.
2) Can you kindly let us know more on the read failures. Is only address 0 is failing or any other address is failing as well. Also how many devices is showing this behavior.
3) Can you pass us the scope shots of read and write waveforms to the hyperram with only the control signals and data signals of the hyperram and remove other signals. This way we will be able to understand the issue more elaborately.
4) Are you able to read the Configurations registers of the device successfully or is it also giving error. Please pass on the values that you are reading from the CR0 and CR1 registers.
Thanks for your reply.
1) Yes I attached related parts.
2) it fails with other address also, always like random but data stay the same after power cycle for each board, that's strange. I test on 3 boards, the same behavior.
3) please see attached doc.
4) I did tried reading ID0, but got the same data as reading from memory.
If I hold reset at low, I will read all 0 values which is reasonable to me, and also it looks rwds pin is driven by hyperram from the waveform.
Thanks for your help,
If you are unable to read the device ID from the HyperRam then the connection between the device and the controller has not been setup properly.
1) The HyperRam you are using has a latency of 7 clock cycles by default. What is the latency settings at the controller side.
2) If the latency settings are ok then we will need to verify all the timing specifications as per the datasheet. Since verifying them through logic analyzer will be difficult we need to check all the signals for the Hyper ram through a oscilloscope. We will need to check the power up wave form and then the read id command waveform to understand and verify all the timing parameters. Can you provide us the scope shots for these two as mentioned.
1. I am using the default setting, 7 clock. And also to avoid I miss/overcount the latency clock, I was just looking over the dq_i bus to search for correct data.
2. Sorry, as I said I cannot probe HyperRam pins except DQ7 and DQ6 which showed similar waveform as logic analyzer during reading. That means HyperRam is actually responding and outputting data.
Now I suspect the HyperRAM is not recognizing my command. The controller IP was only verified with 641 device, I will run simulation against 642 device to see if I can find something.
Thanks for your help,