HyperRAm IP-Core FPGA timing closure issue. Help requested

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AlMa_4596461
Level 1
Level 1
Welcome!

Hi,

I am trying to compile the HyperBus Memory Controller IP - Release version V2L4_02  in a Xilinx Artix 7 FPGA device. I get a lot of timing errors. When digging in the design, I see a lot of the failing path that seems to be intended asynchronous as they are re-synchronized. My first guess is most of these timing path should be ignored during the timing analysis and set as false path.  I find it risky to set false path on these failing path as I am not familiar with the design and  I do not want to over-constraint and make Vivado ignore valid timing paths.

The sdc file provided with the IP-Core declares clock domains asynchronous between each others. But deeper in the design, clk and ip_clk domain are connected together in the file rpc2_ctrl_mem.v. By doing so, the 2 clock domains become a unique domain and therefore path between the 2 get analyzed.  I suspect that some unnecessary re synchronization logic should be removed on these path or false path constraints should be added.

As someone encountered such issue? Is it possible to find a list of what should be declared as false path?

Best Regards,

Alain

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1 Solution

Hello Alain,

I extend my sincerest apologies to you. I just recently discovered that the "Private Messaging" component for the Community Forum has been permanently disabled.  Please go to the URL specified directly below to request the HyperBus Memory Controller IP Package :

 

https://www.cypress.com/documentation/software-and-drivers/hyperbus-master-interface-controller-ip-i...

pastedImage_0.png

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

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8 Replies
AlbertB_56
Moderator
Moderator
Moderator
500 replies posted 50 likes received 250 replies posted

Hello Alain,

Thank you for contacting Cypress Semiconductor

I will send you a private message. Please follow the instructions and answer the questions, required for HyperBus Controller registration.

Thank you in advance...

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

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Hello Alain,

Please provide the following information, required for Hyperbus Registration:\

1).  Complete First and Last Name

2).  Name of Company

3).  Complete address and location of Company

4).  Direct contact phone number

5).  Active e-mail address

6).  Cypress/Infineon product Ordering Part Number (OPN) that will be used with the HyperBus Controller

Thank you in advance...

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

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Hi Albert,

Thanks for following up. How do I submit securely the requested information. There is sensible information. Can't  be posted on the forum.

Best regards,

Alain

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Hello Alain,

I extend my sincerest apologies to you. I just recently discovered that the "Private Messaging" component for the Community Forum has been permanently disabled.  Please go to the URL specified directly below to request the HyperBus Memory Controller IP Package :

 

https://www.cypress.com/documentation/software-and-drivers/hyperbus-master-interface-controller-ip-i...

pastedImage_0.png

Best regards,

Albert

Cypress Semiconductor Corp.

An Infineon Technologies Company

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Hi Albert,

Thank you for following up. We already have the IP package. The version we have in house is V2L4_02. Is this the latest version? The issue we have is we are having problem closing timings in an Artix FPGA for running the core at 166MHz. We need more direct support.  What is the best way to proceed?

Best regards,

Alain

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Hello Alain,

With re-registering for the HyperBus Memory Controller IP package, it was with hope we can verify your identity,

as there are more than one "Alain" within our database.

Therefore, to expedite this issue more quickly, please confirm that is your correct e-mail address :  amarchan@matrox.com.

We will then know as to which Case# to associate this issue.

Thank you in advance...

Best regards,

Albert

Cypress SemiconductorCorp.

An Infineon Technologies Company

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Hi Albert

This is correct, this case is for Matrox, and my email is amarchan@matrox.com.

Best regards,

Alain

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Hello Alain,

Thank you for verifying your e-mail adrs. 

I have located your original (case) request, initiated in November, 2019.

This same case will be used for this current issue.

Best regards,

Albert

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