hyperbus DQ wave is abnormal，why？ Please help analyse。
circuit：
hi
Thanks very much for replay.
We have sim, result is OK, drive strength setting is same as sim setting.
when read, the test point is SoC side, clk and DQ1 wave as below.
When write, the test point is flash side, clk an DQ2 wave as below.
CLK is 196MHz.Wave(zoom) as below.
SoC is CYT4DN(Cypress).
Best Regards.
1) 如果把频率降低(如 80MHz 或 50MHz)，波形有无改善？还是有~1V的半波吗?
If the frequency is reduced (such as 80MHz or 50MHz), is the waveform improved? Is there still a half wave of ~ 1V?
2) 请问flash在不操作的时候DQ的状态是floating的吗？对于写操作的这个图来说，当差分时钟不跳变时(主控对flash无操作)flash不会工作，此时为什么DQ线上会被拉高？另外在写的过程中flash不会输出只是被动输入要写的命令地址数据，但是此时主控的信号是~1V左右的半波，这个有些奇怪。
Is the state of DQ floating when flash is not in operation? For the graph of write operation, when the differential clock does not jump (the master control has no operation on the flash), the flash will not work. Why is the DQ line pulled up at this time? In addition, in the process of writing, flash will not output but passively input the command address data to be written, but at this time, the main control signal is about 1V half wave, which is strange.
3） 对于读操作波形，也存在很多差分时钟不跳变时DQ依然为高电平的情况，会不会存在多个master同时访问同一slave的情况？这样可能会产生波形叠加及半波的可能性。
For the read operation waveform, there are many cases where DQ is still high when the differential clock does not jump. Will there be multiple masters accessing the same slave at the same time? This may result in the possibility of waveform superposition and half wave.
hi, Roy
这批板都是这样的问题。
layout是按照guide来，等长和阻抗匹配50Ω都有遵守。
昨天有抓取了，write，SCK/#CS/DQ1/DS一开始的信号波形及局部扩大图。
背景：
目前其实senmper flash这个功能，软件还没实现。
因为硬件要先检证，所以软件帮忙做了测试软件，如下：
Flash // Launch Semper Flash mode.
Flash_EWR_Random // Flash Erase-Write-Read(verify) for random data
Flash_EWR_55 // Flash Erase-Write-Read(verify) for all AA data
Flash_EWR_AA // Flash Erase-Write-Read(verify) for all 55 data
Flash_Erase // Comming soon!!
Flash_Write // Comming soon!!
Flash_Read // Comming soon!!
发一个简单命令，会有数据产生，这样抓取波形检证，这个时候发现的问题。
以上 谢谢。
