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Do you need to know which Infineon memories have been qualified with which Xilinx FPGAs, and what design tools are available? Infineon has collaborated with Xilinx to not only provide robust solutions that simplify your design process, but we have now created a new Xilinx solutions summary product brief that displays all the NOR Flash memory supported by Xilinx Vivado Design Suite.
The product brief lists Flash and RAM memories that have been qualified with Xilinx FPGA and FGPA+SoC products, and also summarizes other Infineon tools (drivers, memory controller IP, U-Boot patches, etc.) that are available to help you get to market quickly. The Xilinx solutions summary is our first product brief, with more to follow, so stay tuned to our blog!
To access this product brief pictured below, please view the attached .pdf to this blog post.
Why did the Eclipse IDE for ModusToolbox quit unexpectedly on my macOS Big Sur machine?
For some macOS machines running on M1 processors, the Eclipse IDE may fail to start with a message such as:
"ModusToolbox quit unexpectedly."
The message details also state that the "attachment of code signature supplement failed."
This problem occurs any time that Eclipse was last opened in an empty workspace prior to a reboot. After the reboot, the application fails to start.
Run the following command in the /Applications/ModusToolbox/ide_x.y/ModusToolbox.app directory:
xattr -dr com.apple.quarantine *
You may have to adjust the path if you installed ModusToolbox in a non-default location.
When complete, launch the Eclipse IDE again. This workaround works for all cases so far discovered.
How to use non-blocking method instead of blocking method in PSoC™ 4 flash?
When executing flash erase or write action, the low-level driver uses blocking write method, disables all CPU interrupts until the end of the operation. Sometimes, the system needs to use non-blocking write. The following steps show how to use the non-blocking method using the CY8CKIT-041 Demo Kit:
1. Add the following lines of code to main.c, and make sure to set IMO to 48 Mhz in the *.cydwr clocks.
#define SPC_INT_IRQ 9u //the SPC interrupt No. follow the table
PSOC 4100S plus
#define REG(addr) (*((volatile uint32 *) (addr)))
#define CPUSS_CONFIG_REG REG( 0x40100000 )
extern void SpcIntHandler();
/* Set CPUSS_CONFIG.VECS_IN_RAM because SPC ISR should be in SRAM */
CPUSS_CONFIG_REG |= 0x00000001;
2. Go to Project → Build Settings. In the Build Settings dialog, set Skip Code Generation to False. Then, compile the project to generate the low-level driver.
.data : ALIGN(8)
__cy_region_start_data = .;
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN (8);
. = ALIGN (8);
_edata = .;
} >ram AT>rom
4. Define and assign the following three functions to the RAM section of the flash.c file.
/* Variable to keep track of how many times SPC ISR is triggered */
uint32 iStatusInt = 0;
volatile uint32 parameters;
/* Write key1, key2 parameters to SRAM */
parameters[0u] = (uint32) (((uint32) CY_FLASH_KEY_TWO(0x09) << CY_FLASH_PARAM_KEY_TWO_OFFSET) | CY_FLASH_KEY_ONE);
/* Write the address of key1 to the CPUSS_SYSARG arg */
CY_FLASH_CPUSS_SYSARG_REG = (uint32) ¶meters[0u];
/* Write the API code = 0x09 to the CPUSS_SYSREQ.COMMAND
* register and assert the sysreq bit */
CY_FLASH_CPUSS_SYSREQ_REG = CY_FLASH_CPUSS_REQ_START | 0x09;
/* Number of times the ISR has triggered */
* Function Name: CySysFlashWriteRow
* Erases a row of Flash and programs it with the new data
uint32 CySysFlashWriteRow(uint32 rowNum, const uint8 rowData)
5. Set the other interrupt, such as the 2 ms timer interrupt service routine in main.c,. Add the following code. The CPU will run into this handler every 2 ms.
/* Clear the TCPWM terminal count interrupt */
if(msCount >= 2)//////1000
/* Toggle the green LED state */
msCount = 0;
secFlag = 1;
Assign the API in the interrupt handler to the RAM:
6. In the Build Settings dialog, set Skip Code Generation to True. Then, compile the project.
7. Download the hex to the chip. The blue and red lights will be ON without any blinking. If using the blocking mode, the light will blink because the CPU could not operate flash when it is writing or erasing. Then, the timer interrupt handler will be pending until the operation finishes. The minimum time of flash operation should be 15 ms to 20 ms.
In response to the previous (locked) thread
Please consider removing the title altogether in all posts as unnecessary. Adding title to every post looks odd, takes space and bears no information.Show Less
Sectors are the erase units of a flash memory. Infineon serial NOR flash devices offer a flexible sector architecture with two options:
Whether a device supports hybrid sector architecture or not can be determined through the model number in the ordering part number (OPN) of the device or the configuration register settings. See the respective device datasheet for detailed OPN definition including model number information.
Configuration register settings can be modified to change the default sector architecture. For example, in the FS-S device family, one particular bit of the configuration register (CR3NV ) enables or disables the 4-KB parameter sectors. The default state of CR3NV bit is 0, which means 4-KB sectors are enabled. The configuration register can be programmed to set the CR3NV bit to 1 to disable 4-KB parameter sector overlay and choose the uniform sector size option. The CR3NV bit is an OTP (one time programmable) bit, which means it can be programmed only once in the entire lifecycle of the flash memory.
4-KB parameter sectors can be at the bottom or top of the flash device. Their location can be changed by modifying the TBPARM bit of the configuration register. TBPARM is also an OTP bit. For example, the default value of the TBPARM bit is 0, indicating that the 4-KB physical sectors are located at the bottom (low address). Programming the configuration register to set TBPARM bit to ‘1’ will change the location of the parameter sectors to top (high address) space.
There are special commands to perform sector erase operation on these 4-KB parameter sectors. The P4E (20h) and the 4P4E (21h) commands can be used to erase parameter sectors. The P4E command can take 3-byte as well as 4-bytes address, whereas the 4P4E command always expects 4-bytes address. The P4E and 4P4E commands are ignored when the device is configured for uniform sector size option.
Sector organization in FL-S and FS-S devices –
In FL-S device, the 64-KB sector erase command (D8h or DCh) can also be used to erase a group of sixteen 4-KB parameter sectors. The advanced sector protection feature provides a PPB and a DYB protection bit for each of these thirty-two 4-KB parameter sectors. If the 64-KB sector erase command is applied to a certain 64-KB range such that it includes a protected 4-KB sector, the erase operation will not be executed on the protected range of memory and the E_ERR bit in the status register will be set.
On the other hand, in the FS-S family, only the parameter sector erase commands (20h or 21h) must be used to erase 4-KB sectors individually. The uniform sector erase command (D8h or DCh) should be used to erase all remaining sectors (224-KB sector and 256-KB sectors). The same conditions are applicable for 128Mb/256Mb FS-S device parameter sector and uniform sectors (32-KB sector and 64-KB sectors) as well.
This project was submitted by @Vinayyn in The Infineon Great PSoC 6 Design Challenge with Mouser and Electromaker.io and was one of the winners!
Project Technology Focuses
This end-end proof of concept (PoC) Smart Home project aims to bring to life multiple common, automated functions you’d see in that type of environment. The PSoC 6 WiFi-BT Pioneer Kit was used along with multiple sensors to implement: CapSense capacitive-sensing for touch UI in appliances, intruder detection and alert using motion sensor, noise detection via PDM Mic, light control via ambient light sensing, and more. This sensor data was aggregated and alerts are displayed on the kit’s TFT display via emWin software libraries and transmitted to an AWS dashboard via on-board Wi-Fi.
This project was submitted by @Knaveen in The Infineon Great PSoC 6 Design Challenge with Mouser and Electromaker.io and was one of the winners!
Project Technology Focuses
This innovative project implements voice recognition at the edge for an IoT Node using the PSoC 63 MCU with Bluetooth LE connectivity implemented. The developer creating this project generated and trained a voice recognition model to take action off of specific keywords commonly used in home automation type applications – and then deployed it on the PSoC 6 MCU using ModusToolbox. PSoC 6 would send Bluetooth LE transmissions to a peripheral upon recognition of certain commands – for example “Turn On/Off AC!”.
This project was submitted by @Bastiaan Lee in The Infineon Great PSoC 6 Design Challenge with Mouser and Electromaker.io and was one of the winners!
Project Technology Focuses
This project consists of implementation a very robust audio processing program on PSoC 6 – taking advantage of its peripherals as well as enablement in ModusToolbox to make an IoT Audio Sensor node application. The program records audio samples with the PDM microphone on the PSoC 6 WiFi-BT Prototyping Kit, converts that to PCM data which then going through a Fast Fourier Transform with HANN windowing, to be able to split the audio data into octaves. Based on A/C/Z weighting, the audio data is then further calculated into data that represents what our ears do actually hear. This audio data is transmitted via Wi-Fi and graphed on a series of easy-to-use dashboard as well.
During semester one, first year students from the Electronic Engineering and Mechanical Engineering courses at Letterkenny Institute of Technology undertake the Bluetooth Low Energy (BLE) Robot Build & App Development project as part of the Introduction to Electronic Engineering module.
Each student builds their own Bluetooth controlled robot and develops an app for their Android or iOS smartphone or tablet to control the robot. The PSoC 4 BLE microcontroller by
Cypress Semiconductor Corporation (Cypress.com) an Infineon technology company, is the brain of the robot. The Cypress PSoC 4 BLE device is a programmable embedded system-on-chip that integrates a Bluetooth Low Energy (BLE) radio.
Students were allocated 4 hours for app development and 2 hours for robot build & test, completed over the duration of the semester under the guidance of Electronics Lecturer Martin Bradley and Senior Technical Officer James Molloy.
Youtube video link: https://youtu.be/_TmaJWldHnE