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Ever wonder how long Infineon plans to support each of its NOR Flash memory solutions? Or what other products are available in the portfolio?
That information can easily be found on the Cypress website, which has product roadmaps for all NOR Flash products – including separate ones for automotive. NOR Flash roadmaps have been updated for Q3, and detail the entire portfolio of serial and parallel Flash memory solutions.
Download and view Infineon NOR Flash roadmaps now. And while you’re at it, feel free to explore the other Cypress roadmaps posted there too!
Follow these options to optimize your SEMPERTM Flash Memory program and erase performance:
Question: Is there a potential for the AUTOSTORE cycle to be interrupted if a brownout occurs between 25 ns – 8 ms and will a potential data loss occur?
AutoStore operation will be uninterrupted if the power provided by the AutoStore capacitor connected to the VCAP pin matches the datasheet specifications; hence there is no potential for data loss. For details about nvsRAM features, refer to the specific device datasheet.
The device will complete the ongoing AutoStore cycle and initiate power-up RECALL process even if it is interrupted by power-up cycle. When the voltage on the VCC pin drops below VSWITCH during power-down, the device automatically performs AutoStore operation using the voltage from the VCAP capacitor. Note that the AutoStore operation is initiated only if a Write operation has been performed since the last STORE operation (see Figure 1).
Figure 1. AutoStore or Power-Up Recall
Question1: How do you power USB I/O when FX3 is used as a self-powered device?
Answer: The USB I/O requires a 3.3-V regulated power supply. This supply is internally driven from either the VBUS or VBATT external supplies. If the USB port is used, one or both supplies must be present. For an FX3 self-powered design, VBATT can be connected to the system battery or a stable 3.2 V–6 V voltage rail from the PMIC; the VBUS pin of FX3 can be connected to VBUS of the USB connector to detect the upstream USB connection. If VBUS and VBATT are both present and in their specified ranges, VBUS becomes the primary supply to the USB I/O; the FX3 device draws power from the VBUS supply by default unless there is a software/firmware override. FX3’s USB block can be configured to work off VBATT power instead of VBUS using the CyU3PUsbVBattEnable API. Please refer to the FX3 API Guide from the FX3 SDK for more details about the API.
Question2: What firmware changes are needed when FX3’s VBUS pin is not connected to the USB connector’s VBUS signal?
Answer: When the FX3 is functioning as a USB device, it performs VBUS detection by default and will connect to the host only when VBUS voltage is above 4.1 V. When FX3’s VBUS is left unconnected, the user is expected to enable/disable the USB connection in firmware at appropriate times. In this case, both the enable and useVbatt parameters of the CyU3PUsbControlVBusDetect API should be set to CyFalse, and the CyU3PConnectState API should be called directly by the user application. As mentioned in Question1, use the CyU3PUsbVBattEnable API to have the device draw power from VBATT instead.
Note: If FX3’s PMODE lines are configured for USB boot (Z11) and VBUS pin is not connected to the USB connector’s VBUS signal, the device will not enumerate. In this case, it is recommended to configure the PMODE lines for boot options other than USB boot.
Question: What are the source and sink charging specifications in CCG3PA?
Answer: The following table lists the source and sink charging specifications in CCG3PA:
Part 1: CYPD3171
CCG3PA does not support USB-PD 3.0 PPS in the sink role because QC 2 and QC 3 sink are based on Dp-Dm line voltages and QC4.0 protocol uses USB-PD 3.0 PPS.
Part 2: CYPD3174
Part 3: CYPD3175
Question: What should I do if power-fail interrupt (PFI) is detected in HyperRAM™ devices?
Answer: Power-fail interrupt (PFI) is detected in two cases:
Voltage in the VCC pin drops below VRST (0.7 V) level. In this case, the voltage in VCC pin must be below VRST level for a minimum time period of Tpd time. Normal power initialization can be performed when this timing is followed.
If the voltage in VCC pin rises above VRST (0.7 V) level before Tpd time, then perform hardware Reset for proper initialization of the chip.
Voltage in the VCC pin drops below VCC Min. (0.7 V) level but never drops below VLKO level. In this case, the part will remain initialized and functions accurately when VCC rises again above VCC Min. For more details, refer the specific device datasheet (see Figure 1).
Figure 1. Power-Down or Voltage Drop
Question: CS# is at a logic low state but has not yet delivered an SPI command nor a clock signal to the SPI NOR flash memory. However, a leakage current occurred. Is this normal behavior?
Answer: When the CS# signal is at the logic high state, the device is not selected and all output signals are high impedance. Then the device will be in the Standby Power mode unless an internal embedded operation is in progress. But driving the CS# input to the logic low state puts the device in the Active Power mode, even there is no clock input nor any SPI command. Thus it is observed as if there is a leakage current.
Author: Ashwin Nair Version: **
The EZ-USB™ FX3 Explorer kit can be used as a 16-channel 100 MHz USB 3 logic analyzer with sigrok PulseView. (Note that the following steps are applicable for any FX3 device. Explorer kit is used in this KBA, as all the IOs needed are exposed in this kit as shown in Figure 1).
This KBA lists the steps required to use the FX3 Explorer kit as a logic analyzer with PulseView.
Figure 2. cypress-fx3 in the list of supported hardware devices
Figure 3. Download Image file to onboard I2C EEPROM
Figure 4. Bind FX3 device to WinUSB
Figure 5. Scan for cypress-fx3 devices
Figure 6. Using SPI Decoder to decode captured signals
Download the following files from FX3.zip:
The Motorola SPI protocol has four different modes based on how data is driven and captured on the MOSI and MISO lines. These modes are determined by clock polarity (CPOL) and clock phase (CPHA). Clock polarity determines the value of the SCLK line when not transmitting data. CPOL = '0' indicates that SCLK is '0' when not transmitting data. CPOL = '1' indicates that SCLK is '1' when not transmitting data. Clock phase determines when data is driven and captured. CPHA=0 means sample (capture data) on the leading (first) clock edge, while CPHA=1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising or falling. With CPHA=0, the data must be stable for setup time before the first clock cycle.
CY8CKIT-042, PSoC Creator 4.3 (188.8.131.525) used to test, set SPI Bit order to MSB, send the first 8-bit data 0x01.
Mode 0: CPOL is '0', CPHA is '0':
Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK. Timing in SPI Component is shown in Figure1. The actual operation sequence is shown in Figure 2.
Figure 1. Timing in SPI Component
Figure 2. Timing in actual operation
Mode 1; CPOL is '0', CPHA is '1'
Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK. Timing in SPI Component is shown in Figure 3. The actual operation sequence is shown in Figure 4.
Figure 3.Timing in SPI Component
Figure 4. Timing in actual operation
Mode 2: CPOL is '1', CPHA is '0'
Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK. Timing in SPI Component is shown in Figure5. The actual operation sequence is shown in Figure 6.
Figure 5. Timing in SPI Component
Figure 6. Timing in actual operation
Mode 3: CPOL is '1', CPHA is '1'
Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK. Timing in SPI Component is shown in Figure7. The actual operation sequence is shown in Figure 8.
Figure 7. Timing in SPI Component
Figure 8. Timing in actual operation
As a conclusion, when the SPI bus starts to transmit data, the MOSI will be driven before the SS is effective. This design conforms to SPI protocol and can communicate normally.
Here, the MOSI drive mode has been configured to “strong drive” mode during the firmware startup in cyfitter_cfg.c. If the SPI interface is used to simulate other communication protocols, the starting sequence should be taken into consideration.