- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
I'm otpimizing my linker script for the MB9BF321K and I was wondering what the difference was between the SRAM0 and SRAM1.
I do know that SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core and SRAM1 is connected to System bus. But in the standard linker file the SRAM1 isn't used.
When should SRAM 0 or 1 be used? What can they not be used for? What is the difference? And what advantage does one have over the other?
It's a shame to have an extra 8kB of RAM where I can't find a purpose for.
Gr.
Tom
Solved! Go to Solution.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Tom,
Sorry for the late response.
Both SRAMs can be used for code execution and data storage, but there are few things to mention:
- SRAM1 ist not directly connected to I- and D-Bus, thus code execution might be slightly slower.
- When using both SRAMs for data storage, a variable should not be placed partially in both SRAMs.
For example : 32bit access to 0x1FFF_FFFD
Expected access : 0x1FFF_FFFD, 0x1FFF_FFFE, 0x1FFF_FFFF, 0x2000_0000
Real access : 0x1FFF_FFFD, 0x1FFF_FFFE, 0x1FFF_FFFF, 0x0000_0000 (wrap around)
See also Chapter 14.9 in: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337e/DDI0337E_cortex_m3_r1p1_trm.pdf
Because of the second behavior and the precautions that have ot be made SRAM1 is not used in the default linker files.
kind regards,
Achim
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Cypress crew?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello Tom,
Sorry for the late response.
Both SRAMs can be used for code execution and data storage, but there are few things to mention:
- SRAM1 ist not directly connected to I- and D-Bus, thus code execution might be slightly slower.
- When using both SRAMs for data storage, a variable should not be placed partially in both SRAMs.
For example : 32bit access to 0x1FFF_FFFD
Expected access : 0x1FFF_FFFD, 0x1FFF_FFFE, 0x1FFF_FFFF, 0x2000_0000
Real access : 0x1FFF_FFFD, 0x1FFF_FFFE, 0x1FFF_FFFF, 0x0000_0000 (wrap around)
See also Chapter 14.9 in: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337e/DDI0337E_cortex_m3_r1p1_trm.pdf
Because of the second behavior and the precautions that have ot be made SRAM1 is not used in the default linker files.
kind regards,
Achim